Chow, Chun Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 82-89). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background and Motivation --- p.1 / Chapter 1.2 --- Objective --- p.2 / Chapter 1.3 --- Contributions --- p.2 / Chapter 1.4 --- Organization of the Dissertation --- p.3 / Chapter 2 --- Carbon Nanotubes as Sensing Elements --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Introduction to Carbon Nanotubes --- p.5 / Chapter 2.3 --- Fabrication of Single Carbon Nanotube Sensors --- p.6 / Chapter 2.4 --- Batch Fabrication of CNT Sensors using Dielectrophoretic Force --- p.7 / Chapter 2.4.1 --- Basic CNTs Sensor Fabrication Process using DEP Process --- p.7 / Chapter 2.4.2 --- Modification of Fabrication Process --- p.9 / Chapter 2.5 --- Noise in Resistors --- p.9 / Chapter 2.5.1 --- Thermal Noise in Traditional Resistors --- p.10 / Chapter 2.5.2 --- Flicker Noise (1/f )Noise in Traditional Resistors --- p.11 / Chapter 2.6 --- Noise in CNTs Resistors --- p.11 / Chapter 2.6.1 --- Literature Review --- p.11 / Chapter 2.6.2 --- Noise in CNT Sensors Fabricated using DEP Process --- p.12 / Chapter 2.7 --- CNT Sensors --- p.16 / Chapter 2.7.1 --- Pressure Sensors --- p.17 / Chapter 2.7.2 --- Fluid-Flow Sensors --- p.18 / Chapter 2.7.3 --- Alcohol Sensors --- p.18 / Chapter 2.8 --- CNT Sensor Response --- p.19 / Chapter 2.8.1 --- Traditional Sensor Response Measurement Techniques . . . --- p.19 / Chapter 2.9 --- Accuracy of CNT Sensor System --- p.22 / Chapter 2.10 --- Summary --- p.24 / Chapter 3 --- Design and Analysis of a CNT-CMOS Integrated Sensor --- p.25 / Chapter 3.1 --- Introduction --- p.25 / Chapter 3.2 --- Introduction to CNT-CMOS Integration --- p.26 / Chapter 3.2.1 --- Difficulties with Commercial CNT Sensors --- p.26 / Chapter 3.2.2 --- Novel Idea for CNT-CMOS Integration --- p.26 / Chapter 3.3 --- Design and Analysis of a CNT-CMOS Sensor Prototype --- p.27 / Chapter 3.3.1 --- Goals of CNT-CMOS Integrated Sensor --- p.27 / Chapter 3.3.2 --- Architecture of CNT-CMOS Sensor --- p.28 / Chapter 3.3.3 --- Programmable Current Source --- p.29 / Chapter 3.3.4 --- Dual Slope ADC --- p.41 / Chapter 3.3.5 --- Power Consumption of CNT-CMOS IC --- p.53 / Chapter 3.3.6 --- Electrodes for CNT Sensor Formation --- p.53 / Chapter 3.3.7 --- Electrostatic Discharge Protection and Layout of Prototype --- p.56 / Chapter 3.4 --- Alcohol Tester --- p.60 / Chapter 3.4.1 --- Operation of Alcohol Tester --- p.60 / Chapter 3.5 --- Summary --- p.61 / Chapter 4 --- Results --- p.63 / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Chip Package and Photography --- p.63 / Chapter 4.3 --- Results from Programmable Current Source --- p.65 / Chapter 4.3.1 --- Temperature Coefficient --- p.65 / Chapter 4.3.2 --- Output Resistance --- p.66 / Chapter 4.4 --- Results from Dual Slope ADC --- p.67 / Chapter 4.5 --- Power consumption of the Integrated Circuit --- p.72 / Chapter 4.6 --- CNT Sensor Formation --- p.72 / Chapter 4.6.1 --- Noise Measurement of CNT-CMOS Integrated Sensor --- p.76 / Chapter 4.7 --- Alcohol Tester Results --- p.76 / Chapter 4.7.1 --- Carbon Resistor --- p.77 / Chapter 4.8 --- Summary --- p.77 / Chapter 5 --- Conclusion --- p.79 / Chapter 5.1 --- Future Work --- p.80 / Chapter 5.1.1 --- Detailed CNT Noise Characterization --- p.80 / Chapter 5.1.2 --- High Frequency CNT Measuring Technique --- p.81 / Chapter 5.1.3 --- Higher Degree of CMOS Integration --- p.81 / Chapter 5.2 --- Concluding Remarks --- p.81 / Bibliography --- p.82 / A Schematic Diagram of ADC Testing --- p.90

A scalable macromodel for substrate noise coupling in lightly doped substrates with and without a buried layer has been developed. This model is based on Z-parameters and is scalable with contact size and separation. This model requires process dependent parameters that can be extracted easily from a small number of device simulations or measurements. Once these parameters are known, the model can be used for any spacing between the injecting and sensing contacts and for different contact geometries. The model is validated with measurements for a lightly doped substrate with a buried layer and predicts the substrate resistance values to within 12%. The substrate resistances obtained using the model are also in close agreement with the three-dimensional simulations for a lightly doped substrate. / Graduation date: 2003

A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-��m quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD) is -81dB and -65dB with an input signal frequency of 100KHz and 10MHz, respectively. This is the best performance reported to date for a CMOS implementation. / Graduation date: 2003

An analysis that accounts for the effect of standard electrostatic discharge (ESD) structures on critical LNA specifications of noise figure, input matching and gain is presented. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. Two LNAs, one with ESD protection and one without, which operate at 2.4 GHz have been fabricated in a 0.l5��m CMOS process. The LNAs feature one of the best reported performances for CMOS LNAs to date. The LNA with ESD protection achieves a gain of 12dB, a NF of 2.77dB and an IIP3 of 2.4dBm with a power consumption of 4.65mW. The LNA without ESD protection achieves a gain of 14dB, a NF of 2.36dB and an 11P3 of -2.2dBm with a power consumption of 4.65mW. / Graduation date: 2002

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 53-54).

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 98-102).

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 97-101).

Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16683. / Summary in Italian and English; text in English. Includes bibliographical references (p. 171-177).

Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 16228. / Summary in German and English, text in English. Includes bibliographical references (p. 123-132).

M.S. / Computer Science / Software has been developed to analyze the power requirements of NMOS integrated circuits. Power usage is calculated for the entire chip. Current flow through each metal segment of VDD and GND lines is also calculated. The program, Pwranal, takes CIF format files as input and analyzes DC power requirements in the IC. Power estimates are worst case numbers. Power requirements may be less than the estimate but will not be more. Heuristics based on circuit topology are used to generate a more refined estimate of power needs. Initial values of nodes can be specified to provide an even more refined worst case power estimate. Current density is calculated and warning messages are displayed when it exceeds safe values. Maximum voltage drop in the VDD and GND lines is also calculated. An output summary is sent to the terminal. An optional CIF format output file can also be generated that contains detailed information about power distribution within the circuit.