Thesis--PlanA (M.S.)--University of Wisconsin--Stout, 1999. / Includes bibliographical references.

Thesis (M.A.)--University of Hong Kong, 2002. / Includes bibliographical references (leaves 55-57) Also available in print.

Silicon interposers with TSVs (through-silicon-vias) have been developed in single-crystalline silicon wafer to achieve the high I/O (Input/Output) density. However, single-crystalline silicon interposers suffer a few problems such as cost, electrical performance and reliability. To overcome these shortcomings, an entirely different approach using polycrystalline silicon interposers with thick polymer liners are proposed by Georgia Tech Packaging Research Center, aiming to achieve lower cost silicon interposers with high performance and reliability. The objective of this research is to explore and demonstrate thin polycrystalline silicon as a suitable interposer material to achieve high performance and high reliability TPVs (through-package-vias) in polycrystalline silicon materials with lower cost. Three fundamental challenges were defined, including: 1) low resistivity of the polycrystalline silicon, resulting in high electrical loss; 2) reliability problems resulting from CTE (coefficient of thermal expansion) mismatch between silicon and Cu, and 3) handling and processing of thin silicon panels. A three-dimensional EM (electromagnetic) model was developed to simulate insertion loss and crosstalk of TPVs and compared with TSVs. It has been shown thick polymer liner is effective in addressing the fundamental challenge of low resistivity for the polycrystalline silicon material, leading to better electrical performance of TPVs than TSVs. Parametric studies indicate that thicker sidewall liners result in better electrical performance. A two-dimensional axisymmetric model was established to simulate the first principal stresses in silicon and shear stresses in TPV under thermal cycling. TPVs with thick polymer liners present both smaller principal stresses and shear stresses than TSVs due to the low modulus of polymer. Parametric studies suggest that sidewall liners act as stress buffers and thicker liners result in better mechanical performance. Design guidelines based on simulation results were used in TPV demonstration and test vehicle fabrication. Fracture strength of polycrystalline silicon panel has been fundamentally studied with four-point bending tool and Weibull plot. Surface polymer liners on both sides were introduced to improve the handling of thin silicon panels. Quantitative study showed higher characteristic fracture strength for the panel with surface liners than raw silicon panel. Low cost and double-side processes have been developed for TPV fabrication including UV (ultraviolet) lasers for TPV formation, double laser method for liner fabrication and electroless Cu for seed formation. Key steps and mechanisms for aforementioned processes were summarized and discussed. Polycrystalline silicon interposers with TPVs and up to four metal RDLs (re-distribution layers) were designed, fabricated and characterized. Measurement results showed low insertion loss for both TPVs and CPW (co-planar waveguide) transmission lines. Good model to hardware correlation was also observed. Reliability test vehicles of polycrystalline silicon interposers were also designed and fabricated for thermal cycling test. TPVs survived 4000 cycles without significant resistance changes. SEM imaging on the cross-section of the samples confirmed no Cu or silicon cracking. Magnified images around corner also suggested good adhesion at Cu/liner and silicon/liner interfaces.

This dissertation presents several cost-effective production test solutions using fault grading and mixed-signal design verification cases enabled by analog behavioral modeling. Although the latest System-on-Chip (SOC) is getting denser, faster, and more complex, the manufacturing technology is dominated by subtle defects that are introduced by small-scale technology. Thus, SOC requires more mature testing strategies. By performing various types of testing, better quality SoC can be manufactured, but test resources are too limited to accommodate all those tests. To create the most efficient production test flow, any redundant or ineffective tests need to be removed or minimized. Chapter 3 proposes new method of test data volume reduction by combining the nonlinear property of feedback shift register (FSR) and dictionary coding. Instead of using the nonlinear FSR for actual hardware implementation, the expanded test set by nonlinear expansion is used as the one-column test sets and provides big reduction ratio for the test data volume. The experimental results show the combined method reduced the total test data volume and increased the fault coverage. Due to the increased number of test patterns, total test time is increased. Chapter 4 addresses a whole process of functional fault grading. Fault grading has always been a ”desire-to-have” flow because it can bring up significant value for cost saving and yield analysis. However, it is very hard to perform the fault grading on the complex large scale SOC. A commercial tool called Z01X is used as a fault grading platform, and whole fault grading process is coordinated and each detailed execution is performed. Simulation- based functional fault grading identifies the quality of the given functional tests against the static faults and transition delay faults. With the structural tests and functional tests, functional fault grading can indicate the way to achieve the same test coverage by spending minimal test time. Compared to the consumed time and resource for fault grading, the contribution to the test time saving might not be acceptable as very promising, but the fault grading data can be reused for yield analysis and test flow optimization. For the final production testing, confident decisions on the functional test selection can be made based on the fault grading results. Chapter 5 addresses the challenges of Package-on-Package (POP) testing. Because POP devices have pins on both the top and the bottom of the package, the increased test pins require more test channels to detect packaging defects. Boundary scan chain testing is used to detect those continuity defects by relying on leakage current from the power supply. This proposed test scheme does not require direct test channels on the top pins. Based on the counting algorithm, minimal numbers of test cycles are generated, and the test achieved full test coverage for any combinations of pin-to-pin shortage defects on the top pins of the POP package. The experimental results show about 10 times increased leakage current from the shorted defect. Also, it can be expanded to multi-site testing with less test channels for high-volume production. Fault grading is applied within different structural test categories in Chapter 6. Stuck-at faults can be considered as TDFs having infinite delay. Hence, the TDF Automatic Test Pattern Generation (ATPG) tests can detect both TDFs and stuck-at faults. By removing the stuck-at faults being detected by the given TDF ATPG tests, the tests that target stuck-at faults can be reduced, and the reduced stuck-at fault set results in fewer stuck-at ATPG patterns. The structural test time is reduced while keeping the same test coverage. This TDF grading is performed with the same ATPG tool used to generate the stuck-at and TDF ATPG tests. To expedite the mixed-signal design verification of complex SoC, analog behavioral modeling methods and strategies are addressed in Chapter 7 and case studies for detailed verification with actual mixed-signal design are ad- dressed in Chapter 8. Analog modeling effort can enhance verification quality for a mixed-signal design with less turnaround time, and it enables compatible integration of the mixed-signal design cores into the SoC. The modeling process may reveal any potential design errors or incorrect testbench setup, and it results in minimizing unnecessary debugging time for quality devices. Two mixed-signal design cases were verified by me using the analog models. A fully hierarchical digital-to-analog converter (DAC) model is implemented and silicon mismatches caused by process variation are modeled and inserted into the DAC model, and the calibration algorithm for the DAC is successfully verified by model-based simulation at the full DAC-level. When the mismatch amount is increased and exceeded the calibration capability of the DAC, the simulation results show the increased calibration error with some outliers. This verification method can identify the saturation range of the DAC and predict the yield of the devices from process variation. A phase-locked loop (PLL) design cases were also verified by me using the analog model. Both open-loop PLL model and closed-loop PLL model cases are presented. Quick bring-up of open-loop PLL model provides low simulation overhead for widely-used PLLs in the SOC and enables early starting of design verification for the upper-level design using the PLL generated clocks. Accurate closed-loop PLL model is implemented for DCO-based PLL design, and the mixed-simulation with analog models and schematic designs enables flexible analog verification. Only focused analog design block is set to the schematic design and the rest of the analog design is replaced by the analog model. Then, this scaled-down SPICE simulation is performed about 10 times to 100 times faster than full-scale SPICE simulation. The analog model of the focused block is compared with the scaled-down SPICE simulation result and the quality of the model is iteratively enhanced. Hence, the analog model enables both compatible integration and flexible analog design verification. This dissertation contributes to reduce test time and to enhance test quality, and helps to set up efficient production testing flows. Depending on the size and performance of CUT, proper testing schemes can maximize the efficiency of production testing. The topics covered in this dissertation can be used in optimizing the test flow and selecting the final production tests to achieve maximum test capability. In addition, the strategies and benefits of analog behavioral modeling techniques that I implemented are presented, and actual verification cases shows the effectiveness of analog modeling for better quality SoC products. / text

published_or_final_version / Literary and Cultural Studies / Master / Master of Arts

The HELMHOLTZ package, written in Maple V, is a collection of commands to support research in the variational calculus. These commands include the standard operators on differential forms, Euler-Lagrange operators, homotopy operators, Lie bracket, Lie derivatives, and the prolongation of a vector field. We give a brief introduction to the variational calculus. We describe each of the commands in the HELMHOLTZ package completely along with numerous examples of each. Applications of the package include verification of symmetry groups for differential equations, solving the inverse problem of the calculus of variations, computing generalized symmetries, and finding variational integrating factors. A complete listing of the Maple code for HELMHOLTZ is found in an appendix.

Through my study and observation of American jewelry house Tiffany, I could notice how the iconic little blue box contains not only jewellery but also the brand’s myth. The function of the Tiffany box, goes beyond what we normally associate with packaging as wrapping of a product. Therefore, I question what is the function of packaging in commercial culture. Tiffany’s little blue box not only is the container of jewellery but also of the whole Tiffany brand identity and myth. This brand’s myth is basically illusion. It legitimizes the story by itself. It’s the wholeness. It does not bring up any question, instead, we enjoy the fantasy it generates. To achieve one’s dreams of beauty, self-distinction and love, seems more possible by buying a piece of the brand’s myth. Visual language is commonly used to communicate a myth, since the sensual and artistic language is a persuasive tool when narrating desires and dreams. In this sense, Cindy Sherman’s collaboration with Mac and Marc Jacobs is a good example, which broadens the idea of the so-called ‘aestheticization in commercial culture’. The visual expression of brand myth, was displayed and it has developed into package in the present days. Nowadays, customers are "educated" by commercials to perceive the package as the symbol of brand myth. Packaging is regarded as being as significant as the actual substance of commercial products. Even more so, packaging has become more significant than the actual content. It is more important for brand companies that their customers remember where the product is from, than what it actually is. Since brand packaging has a strong connection with brand jewelleries, the shape of packaging is used as a symbolic language. Norman Weber’s work, ‘jewellery houses’, represents, in this sense, an evident example. Moreover, packaging and jewellery shapes have been used as a symbol of commercial culture; an example of this is evident in Jeff Koons’ works ‘blue diamond’ and ‘hanging heart’. Based on this notion, I combine jewellery and packaging in my work in order to make my own statement about the relationship between packaging and jewellery in commercial culture. I previously stated that packaging related to brand myth, has been growing to the extent that it became more relevant than the actual content in the context of commercial jewellery culture. With my artistic statement about packaging, I am at shaping a critical discussion on the overwhelming illusion of consumption related to brand myth in commercial culture. Keyword: Commercial culture, Aestheticization, Tiffany, Brand fantasy, Visual language, Packaging, identity, Alienation

This study proposes a low cost potentiall with non-AR coated fiber grating external cavity laser (FGECL) module to apply the metro/access network. The components inside the module include uncoated FP (Fiber-Perot) laser chip, PIN detector, substrate, and cooler. The processes of package are following: (1) to utilize the die-bonder to fix the FP laser and the PIN detector on the substrate, (2) to utilize the heating apparatus to make the cooler fixed on the butterfly housing and the substrate fixed on the cooler, (3) to utilize the 353ND paste to make the thermistor fixed on the substrate, and (4) to utilize the electrothermal heating machine to melt indium wire and then adjust the fiber lens provided with higher coupling efficiency of fiber pigtail by tweezer to couple light into the fiber inside the butterfly housing. This study achieves a FGECL module with the output power of larger than 2mW and the side-mode suppression ratio (SMSR) of more than 38dB. Finally, we measure eye diagram and bit-error-rate at 2.5Gb/s of the FGECL module to analyze the impedance matching of laser diode, current signal and the limit of the dispersion to the optical communication system. The performance of the FGECL module can meet the ITU-T G.957 standard.

The main objective of this research is to studying the moisture effect on warpage of PBGA via IR-reflow process by utilizing Shadow Moirè method. The relationship between precondition variations and moisture content of PBGA is also studied.

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