Wireless sensor networks (WSN) have been largely used in various applications due to its ease of deployment and scalability. The throughput of such networks, however, suffers from high bit error rates mainly because of medium characteristics. Maximizing bandwidth utilization while maintaining low frame error rate has been an interesting problem. Frame fragmentation into small blocks with dedicated error detection codes per block can reduce the unnecessary retransmission of the correctly received blocks. The optimal block size, however, varies based on the wireless channel conditions. In addition, blocks within a frame can have different optimal sizes based on the variations on interference patterns. This thesis studies two dynamic partial packet recovery approaches experimentally over several interference intensities with various transmission-power levels. It also proposes a dynamic data link layer protocol: Hybrid Seda (H-Seda). H-Seda effectively addresses the challenges associated with dynamic partitioning of blocks while taking the observed error patterns into consideration. The design of H-Seda is discussed in details and compared to other previous approaches, namely Seda+ and Seda. The implementation of H-Seda shows substantial enhancements over fixed-size partial packet recovery protocols, achieving up to 2.5x improvement in throughput when the channel condition is noisy, while delay experienced decreases to only 14 % of the delay observed in Seda. On average, it shows 35% gain in goodput across all channel conditions used in our experiments. This significant improvement is due to the selective nature of H-Seda which minimizes retransmission overhead by selecting the appropriate number of blocks in each data frame. Additionally, H-Seda successfully reduces block overhead by 50% through removing block number field reaching to better performance when channel conditions are identical.

The thesis deals with the theory and design of the network traffic generator on the FPGA platform. The VHDL programming language is used for the description. The work involves getting acquainted with the development processes and design tools needed to create the overall project. It also includes familiarity with the necessary FPGA, NetCOPE and COMBO cards. Based on this information, was designed, tested and implemented packet generator project for the Combo-80G card. For implementation was used framework from NetCOPE.

This diploma thesis deals with packet classification in computer networks. The problem of packet classification is described, together with requirements for classification algorithm. Then, necessary theoretical background is introduced. Contemporary approaches to the classification are described, together with the critique of the current state of the field. The main focus of the work is the new algorithm of packet classification based on problem decomposition. Unique property of the algorithm is constant time complexity in terms of external memory accesses. Algorithm implemetation is proposed, using FPGA and one external memory. Planned prototype may achieve throughput of 64 Gbit/s in the worst case.

No description available.

No description available.

In a packet radio network, multiple terminals broadcast information over a shared communications medium. Messages are transmitted from a source terminal to a destination terminal over multiple relays or hops. The actions of one terminal in the network directly affect the actions of other terminals within its range. The analysis of packet radio networks is complex because system performance depends on the topology of the terminals in the network along with the random access protocol used. Researchers have been unable to model a packet radio network in its most general form. In this project, a model is developed for specific topologies of a packet radio network with a given random access protocol. The sponsor of this project has developed a packet radio network for an indoor wireless alarm system. At the start of the project, the effect of message collisions on system performance was unknown. As a result of this research, a collision model for the network has been developed for topologies of four, five, and six alarm units. The model has been validated with actual system testing. Furthermore, the effects of indoor propagation on system performance have been studied. The results of this work have led to the development of an installation plan for the indoor wireless alarm system. / Master of Science

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No description available.

This research investigates the application of multiuser interference suppression to direct-sequence code-division multiple-access (DS-CDMA) for peer-to-peer packet radio networks. The emphasis of this work is to develop and validate efficient interference suppression techniques through selective cancellation of interference; next, the combination of interference suppression with error correction coding is studied. A decoder-assisted frame synchronization technique is proposed for future packet radio system. The performance of DS-CDMA in packet radio networks suffers from the near-far problem. This near-far problem can be alleviated by using either a multiuser receiver or a single-user adaptive receiver along with centralized or distributed power control. The first part of this dissertation compares the use of these receivers in a peer-to-peer environment. Next, we investigate how interference cancellation can be combined with forward error correction coding for throughput enhancement of the system. Although receivers using interference suppression are simple in structure, the performance degrades due to the lack of exact knowledge of the interfering signal in cancellation and also due to biased decision statistics for the parallel cancellation case. We consider a system that employs both partial parallel interference cancellation and convolutional coding. Information is shared between the operations of interference cancellation and decoding in an iterative manner, using log-likelihood ratios of the estimated coded symbols. We investigate the performance of this system for both synchronous and asynchronous CDMA systems, and for both equal and unequal signal powers. Finally, a new code-assisted frame synchronization scheme, which uses the soft-information of the decoder, is proposed and evaluated. The sync bits are placed in the mid-amble, and encoded as a part of the data sequence using the error correction encoder to resolve time ambiguities. This technique is applied for turbo decoder-assisted frame synchronization. The performance improvement of these proposed techniques over conventional synchronization techniques is explored via simulation. / Ph. D.

The internet data traffic is tripling every two years due to the exponential growth in the number of routers. Routers implement the packet classification methodology by determining the flow of the packet, based on various rule checking mechanisms that are performed on the packet headers. However, the memory components like TCAMs used by these various rules are very expensive and power hungry. Henceforth, the current IP Lookup algorithms implemented in hardware are even though able to achieve multi-gigabit speeds, yet suffer with great memory overhead. To overcome this limitation, we propose a packet classification methodology that comprises of MicroCuckoo-hash technique, to route packets. This approach alleviates the memory requirements significantly, by completely eliminating the need for TCAM cells. Cuckoo hash is used to achieve very high speed, hardware accelerated table lookups and also are economical compared to TCAMs. The proposed IP Lookup algorithm is implemented as a simulation-based hardware/software model. This model is developed, tested and synthesized using Vivado HLS tool. / Master of Science / The internet data traffic is tripling every two years; due to the exponential growth in the number of routers. Routers implement the packet classification methodology by determining the flow of the packet, based on various rule checking mechanisms that are performed on the packet headers. However, the memory components like TCAMs used by these various rules are very expensive and power hungry. Henceforth, the current IP Lookup algorithms implemented in hardware are even though able to achieve multi-gigabit speeds, yet suffer with great memory overhead. To overcome this limitation, we propose a packet classification methodology that comprises of MicroCuckoo-hash technique, to route packets. This approach alleviates the memory requirements significantly, by completely eliminating the need for TCAM cells. Cuckoo hash is used to achieve very high speed, hardware accelerated table lookups and also are economical compared to TCAMs. The proposed IP Lookup algorithm is implemented as a simulation-based hardware/software model. This model is developed, tested and synthesized using Vivado HLS tool.