The SiC MOSFET has attracted interest due to its superior characteristics compared to its Si counterpart. Several SiC MOSFETs are usually paralleled to increase current capability, considering cost effectiveness and manufacturability. Current unbalance among the MOSFETs is a concern as it affects reliability. The two main causes are asymmetrical layout and parameter mismatch. The variation in parameters, unlike circuit or module layout, is unavoidable during production. Among all the parameters of MOSFET, the spreads in on-state resistance (Rds(on)) and threshold voltage (Vth) are the major concerns during paralleling. The disparity in Rds(on) causes static current unbalance which is self-limited due to the positive temperature coefficient of Rds(on). Its influence is not investigated here. The threshold voltage Vth has a negative temperature coefficient, forcing the MOSFET with lower Vth to carry more current during switching transient. Paralleled MOSFETs are usually de-rated to guarantee safe operation. Balancing of peak currents during switching transient isthe goal of this work. Integration of current/voltage sensors into paralleled structure is difficult in real application. Complicated feedback loop design and separate gate drivers also need to be avoided in perspective of cost and volume. Passive balancing solutions are investigated in this dissertation. The inductors and resistors most effective in improving current sharing are identified by parametric analysis. Their current balancing mechanisms are analyzed in circuit point of view. The design guidelines involving the magnitude of Vth mismatch, current rise time, and unbalance percentage are derived for the selection of passive components. The theory upholds well when substantial parasitics from device package and layout exist. Several passive balancing structures are analyzed and compared in terms of current balancing capability, voltage stress, total switching loss, and switching loss difference. All of them can provide much better current and power balancing without increasing switching loss. Some of the them may increase the stress-inducing inductance, which can be reduced by negative magnetic coupling. Perfect coupling between power-source inductors would enable current matching without penalty on voltage stress. Common-source inductance (Lcm) is effective in dynamic balancing, but at the expense of higher switching loss. It is not considered in power module application because Kelvin connection is normally applied. However, wire bond inside the package of discrete MOSFETs and part of the external leads are inevitable and add to Lcm. Peak-current and switching energy mismatches vary with operating conditions (including input voltage, input current, and switching speed). Design guidelines and procedures that are valid for wide operating range are provided for cases with and without Lcm. This dissertation also models the switching energy and switching energy mismatch of paralleled MOSFETs. The influence of operating conditions, passive balancing components, layout and package parasitic inductances, nonlinear channel performance, and voltage dependent parasitic capacitors are included in the modeling process. The resulting high order system is simplified by reducing the number of passive components and number of devices without losing accuracy. The influence of current balancing components and magnitude of threshold voltage mismatch on sharing are discussed based on modeling results. In conclusion, this dissertation balances the transient currents between paralleled SiC MOSFETs automatically by inductance, resistance and magnetic coupling. This procedure is done utilizing one gate driver without current/voltage sensors and feedback loop. Those solutions work for both polarities of Vth mismatch and force balancing from the first current peak. Design guidelines involving the magnitude of Vth mismatch, current rise time, and maximum peak-current difference are derived to guide the choice of passive components. The detail design procedures are recommended to force currents to share over wide operating range. The aforementioned benefits are demonstrated by two paralleled SiC MOSFETs (C2M0160120D) tested at variant operating conditions. The difference of peak currents can be reduced below 5% of steady-state current in every switching transient. Switching energy mismatch percentage can be reduced by 6 times without increasing total switching energy. / Ph. D. / This research focuses on balancing currents between paralleled SiC MOSFETs. Several SiC MOSFETs are usually paralleled to increase current capability. Current unbalance among MOSFETs caused by variation in parameters is a concern as it affects reliability. Several passive balancing structures are proposed in this dissertation. All of them can provide much better current and power sharing without great scarification of other switching performance. Severity of unbalance varies with operating conditions (including input voltage, input current, and switching speed). Design guidelines and procedures that are valid for a wide operating range are provided. This dissertation also models the switching energy and switching energy mismatch of paralleled MOSFETs. The resulting high order system is simplified by reducing the number of passive components and number of devices without losing accuracy. More findings are discussed based on modeling results. The effectiveness of passive balancing methods are demonstrated by two paralleled SiC MOSFETs tested at variant operating conditions. The difference of peak currents can be reduced below 5% of steady-state current in every switching transient. Switching energy mismatch percentage can be reduced by 6 times without increasing total switching energy.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第24620号 / 工博第5126号 / 新制||工||1980(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 土居 伸二, 教授 小嶋 浩嗣, 准教授 薄 良彦, 教授 引原 隆士 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Silicon carbide (SiC) outperform Si chips in terms of high blocking voltage capability, low on-resistance, high-temperature operation, and high switching frequency. Several SiC MOSFETs are usually paralleled to increase current capability, considering cost effectiveness and manufacturability. For a SiC power module with current rating higher than 100 A, high did/dt and dvds/dt could possibly cause cross-turn-on (crosstalk-induced turn-on) through the gate-to-drain capacitance Cgd of the MOSFET dies and the package inductances. Mismatches in threshold voltage (Vth) up to 33% have been observed among paralleled SiC MOSFETs. This leads to unbalanced transient peak currents and switching energies. Both cross-turn-on and current unbalance degrade the reliability of a power module. Increasing the immunity to cross-turn-on while maintaining the similar switching energies and balancing the transient peak currents below 10% without sacrificing the voltage stress are the goals of this work. Development of a SPICE model free of non-convergence – A simulation model for a SiC power module is necessary for evaluations of cross-turn-on and current unbalance; however, most SiC power modules do not have models. No existing modeling methods discuss how to build an accurate SPICE model that is free of non-convergence when hundreds of parasitic inductances are present. A modeling process is introduced for paralleled MOSFETs encapsulated in a power module that gives access to both the internal channel current and voltage of each bare die inside the package. This model is free of non-convergence and accurate. Parasitic ac resistances, dc resistances, and ac inductances are extracted by Q3D Extractor. Non-convergence is avoided by including the ac resistance of the conduction trace in the model. Also, a series model which is set default in Q3D Extractor is converted to parallel model to accurately reflect how the current flows through the dc and ac resistances of the trace. A complete SPICE model of a commercial SiC power module was derived and validated by experiments. The error between predicted turn-on peak current of the developed model and that of the experimental data is 2%, significantly lower than the 28% difference between prediction result of commercial model and experimental data. Detection of internal cross-turn-on – Terminal current of a power module does not reflect the internal channel current due to the numerous parasitic inductances of the package. No existing method is able to detect the cross-turn-on in a power module since dies are usually encapsulated and the channel currents are hard to measure. A nonintrusive method to identify cross-turn-on based on the changing ringing current is developed. The detection method was analyzed theoretically and validated by experiments using a 1.2-kV SiC module. The negative drive voltage and gate resistance for safe operation can be determined by the detection method. Influence of layout symmetry on immunity to cross-turn-on – Gate resistance, gate-to-drain capacitance of the MOSFET, slew rate of drain-to-source voltage, and temperature have been recognized as the only elements impacting the immunity to cross-turn-on for a single chip and module. Layout symmetry is newly discovered to be another factor that contributes to the immunity. Asymmetrical and symmetrical modules following commercial layouts were tested by a double pulse tester. The peak cross-turn-on currents, high-side switching energy, and total switching energy at various input voltages, low-side gate resistances, and load currents are normalized for comparison. The peak cross-turn-on current of the symmetrical module is 84% lower than that of the asymmetrical module at nominal condition. Longer power-loop and gate-drive loop are required to achieve symmetrical layout for more than two dies in parallel. This increases the low-side switching energy of the symmetrical module. The total switching energies of the two modules are similar. In this case, a symmetrical layout is still recommended since current stress caused by cross-turn-on is much smaller in symmetrical module than in the asymmetrical module and chances to have shoot-through between the high side and the low side are reduced. Magnetic integration into a power module for current balancing – Existing power modules do not have balanced transient currents when threshold voltage mismatch exists. A module with integrated coupled inductors was designed, fabricated, and validated to be effective to balance the currents without sacrificing voltage stress and switching energy. The designed integrated coupled inductors achieve inverse coupling by utilizing the copper trace of the substrate and bond wires and have the following features: size comparable to the silicon carbide (SiC) die, coupling coefficient higher than 0.98, tens of nH operating at tens of MHz, and current rating of tens of Amperes. The coupled inductors with the magnetic material of low-temperature co-fired ceramics (LTCC) are compatible with existing packaging technology for module fabrication. The effectiveness of reducing transient-current mismatch at various input voltages, load currents, and gate resistances was verified by experiments. Compared with the baseline module following commercial practice, the module with integrated coupled inductors reduces current unbalance from 36% to 6.4% and turn-on-energy difference from 28% to 2.6% while maintaining the same total switching energy and a negligible change of voltage stress. / Ph. D. / A silicon carbide (SiC) power module with high di_d/dt and dv_ds/dt could possibly cause crossturn-on (crosstalk-induced turn-on) through the gate-to-drain capacitance C_gd of the MOSFET dies and package inductances. Mismatches in threshold voltage (V_th) up to 33% have been observed among paralleled SiC MOSFETs. This leads to unbalanced transient peak currents. Both crossturn-on and current unbalance degrade the reliability. Increasing the immunity to cross-turn-on while maintaining the similar switching energies and balancing the transient peak currents below 10% without sacrificing the voltage stress are the goals of this work. The development of a SPICE model for a SiC power module is necessary for evaluations of cross-turn-on and current unbalance; however, no existing modeling methods discuss how to build an accurate SPICE model of a power module free of non-convergence when hundreds of parasitic inductances are present. The modeling method to overcome these challenges is introduced. The error between predicted turn-on peak current of the developed model and that of the experimental data is 2%, significantly lower than the 28% difference between prediction result of commercial model and experimental data. No existing method is able to detect the cross-turn-on in a power module since the dies are usually vi encapsulated and the channel currents are hard to measure. A nonintrusive method to identify the cross-turn-on based on the changing ringing current is developed. The detection method was analyzed theoretically and validated by experiments using a 1.2-kV SiC module. Layout symmetry is newly discovered to be another factor that contributes to the immunity. The peak cross-turn-on current of the symmetrical module is 84% lower than that of the asymmetrical module at nominal condition. The symmetrical layout greatly decreases cross-turn-on currents without increasing total switching energy. Power modules in the market cannot have balanced transient currents when mismatches in threshold voltage V_th exist. A module with integrated coupled inductors was designed, fabricated, and validated to be effective to balance the currents with the presence of V_th mismatch. Compared with the baseline module following commercial practice, the module with integrated coupled inductors reduces current unbalance from 36% to 6.4% and turn-on-energy difference from 28% to 2.6% while maintaining the same total switching energy and negligible change of voltage stress.