ABSTRACT In this study, the rf magnetron sputtering was used to deposit (Ba0.8Sr0.2)(Ti0.9Zr0.1)O3 (BSTZ) ferroelectric thin films on SiO2/Si substrates, and MFIS structure was also fabricated. The effects of various sputtering parameters effects on the characteristics of BSTZ thin films, such as the oxygen concentrations, deposition temperature, rf power, chamber pressure and deposition time were be discussed. As deposited on Pt/Ti/SiO2/Si substrate, the electrical and physical properties of BSTZ thin films after RTA and CTA thermal treatment were be also discussed. In XRD and SEM analysis, the crystal structure and grain size of as-deposited BSTZ thin film could be observed. From the C-V and J-E curves obtained, the memory window and leakage current density of MFIS structure were about 9.5V and 2.76¡Ñ 10-9 A/cm2, respectively. After RTA and CTA post-treatment, the capacitances of MFM structure were about 2.06nF and 1.93nF. We found that dielectric constant of as-deposited BSTZ thin film increased to 183 and 194, respectively. In addition, the leakage current density of RTA and CTA treated BSTZ films were about 3.82¡Ñ 10-6 A/cm2 and 1.16¡Ñ 10-6 A/cm2. Finally, the one-transistor-capacitor (1TC) structure of ferroelectric random access memory (FeRAM) with the gate oxide of BSTZ thin films on the polysilicon TFT structure have been fabricated and investigated.From the experimental results, the on/off drain current ratio is two orders, and its value is much smaller than those of the most reported bottom-gated TFTs devices by using different ferroelectric materials as gate oxide. From these results in this study, the BSTZ thin films for top-gate polysilicon thin-film transistor will be an excellent candidate to fabricate higher storage capacitance ferroelectric random access memory (FeRAM) devices for system on panel (SOP) applications.

In this research, the degradation effect of the low temperature polycrystalline silicon TFTs (LTPS TFTs) under dynamic stress was investigated. The experiment results revealed that the degenerate behaviors of n- and p-type poly-Si were different. In p-channel TFT, it was observed that the degradation of threshold-voltage (Vth) was closely associated with the stress frequency of ac stress. The degradation was more serious at low-frequency stress than that at high-frequency stress. The degradation of electrical characteristics of device is mainly dominated by the self-heating enhanced negative bias temperature instability effect. Moreover, the increased temperature around the environment could make the degradation of characteristics more serious, such as Vth shift (fixed charge), degraded S.S (dangling bonds). We suggest that the generation of deep states originated from bond broken at both of grain-boundary and interface state was explained the degradation mechanism of threshold-voltage. In n-channel TFT, the degradation characteristics may be attributed to both of the temperature effect and the hot carrier effect under the different stress frequency. At low-frequency stress, Vth shift (positively) and mobility are increased after 100 seconds stress because of the temperature effect. However, Vth shift (negatively) and mobility are decreased after 500 seconds stress because of the effect of the state creation near the drain regime. At high-frequency stress, the times of the switch is numerous, and result in the on-state current decreased because of the trap state generated.

English Abstract In this thesis, we investigate the electrical properties and reliabilities of poly-Si TFTs for system on panel application. Roughly, we divide the thesis into two parts, n-type and p-type TFTs respectively. In n-type TFT, we mainly study degradation characteristics of TFTs under dynamic stress. On the other hand, we focus on special negative bias temperature instability (NBTI) degradation for p-type poly-Si TFTs. Because grain boundary in poly-Si film and serious self-heating effect due to glass substrate, which has a poor thermal conductivity, the electrical properties and reliabilities of poly-Si TFTs become more complicated, compare with metal-oxide-semiconductor field effect transistor (MOSFET). Therefore, in the thesis, we found some strange phenomena never observed in a-Si TFT and MOSFET. In chapter 3, the degradation mechanism of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated at room temperature under dynamic voltage stress, which simulate under high frequency operation as driving devices. The ON-current of TFT is degraded to as low as 0.3 times of the initial value after 1000 second stress. On the other hand, both the sub-threshold swing and threshold voltage kept well during the AC stress. The current crowding effect was rapidly increased with increasing of stress duration. However, comparing the initial and degraded characteristics at rising temperature, namely, 150◦C, the ON-current of TFT only decrease to 75 percent of the initial value after 1000 second AC stress. It depicts that creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. At high temperature, electron has enough energy to pass the energy barrier created by ac stress and the degradation is less obvious. In chapter 4, the degradation mechanism of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated under dynamic voltage stress, which simulate under low frequency operation as pixel switches. Surprisingly, two totally different degradations of TFTs were observed after dynamic stress. Firstly field-effect mobility and driving current increased during early stress. However, a clear and rapid degradation of field-effect mobility occurred instead during later stress. Additionally, the threshold voltage of stressed TFTs strangely shifted to negative direction in later stress, which was never observed in early stress. Finally, we clarify the degradation mechanisms for early and later stress respectively by varied temperature experiments. In chapter 5, the characteristics of p-type poly-silicon thin film transistor (poly-Si TFT) with dynamic bias stress were investigated. The AC stress is operated with the constant drain voltage (15V) and the varying gate voltage (0V~-15V) to degrade the devices. There are some phenomena which cannot be completely explained by typical NBTI mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could rise channel temperature and cause the dissociation of the Si-H bonds at the poly-Si/SiO2 interface due to the Joule heating. The released hydrogen reacts with SiO2 and causes the fixed charge in the gate oxide. Thus, the degradation of electrical characteristics of device is mainly dominated by the self-heating induced NBTI effect. In chapter 6, we investigate the asymmetric negative bias temperature instability degradation of poly-Si TFTs. Electric measurements of normal and reverse modes were employed to analyze the degradation on Vt, current, leakage current and sub-threshold swing (S.S.). The results indicated that a non-uniform vertical electric field at the poly-Si/SiO2 resulted in asymmetric negative bias temperature instability degradation. The trap generation was a grading distribution from source to drain. Moreover, some energy diagrams were proposed to explain the experimental data. Sequentially, asymmetric TFT degradation resulted from a grading distribution of trap state induced by asymmetric NBTI.

In this thesis, we will investigate the degradation of the low temperature polycrystalline silicon TFTs (LTPS TFTS) under the electrical stress. The electrical stress is divided into two parts of ac stress and dc stress. We used ac stress and dc stress conditions to stress different TFTs respectively and investigate the influence of grain boundary in n-type TFT and p-type TFT by use of electrical analysis. On the other hand, degradation mechanism was confirmed by measured capacitance. In n-type TFT, the SLS poly-Si TFT which contains GB perpendicular to the channel direction owns the higher ability against dc stress and poorer ability against ac stress than the poly-Si TFT which does not contain GB. The physical mechanism for these results has been reasonably deduced by use of TFT device simulation tool (ISE_TCAD). In p-type TFT, the enhancement phenomenon is always observed after dc or ac stress. There are both existed a power-law between the variation of the drain current with stress time. The slope of power-law is related to the shortening speed of effective channel length. In either dc stress or ac stress, there are two effective factors. The one factors of them is the degradation of poly-Si film, and another one is the effective channel length shortening. In the competition of these two effective factors, the GB-TFT has more obvious enhancement than GB-TFT during dc stress. Nevertheless, during the ac stress the GB-TFT is without larger enhancement than NGB-TFT because of serious poly-Si film damage.

In this thesis, the poly-Si TFTs with different channel width and channel length are successfully fabricated and characterized. In particular, by using the T-gate structure and body contact, we can measure the substrate current and body voltage. Therefore, short channel effects in polycrystalline silicon thin-film transistors are investigated clearly. In order to study impact ionization effect and floating body effect more carefully, we measure and compare the electrical behaviors of device with different grain boundary trap density, grain size, and channel dimension. The influences of these factors on the short channel effects are also discussed and explained. In this experiment, it is found that the devices with short channel length, exhibit improved normalized turn on current and smaller threshold voltage. But on the other hand the sever kink effect which generated by the impact ionization also observed. Moreover, the floating body under the channel region serve as a parasitic BJT as in silicon-on-insulator devices. The related single transistor latch-up is observed and discussed for short-channel devices with various channel width. The severe impact ionization effects in polycrystalline silicon thin-film transistors are investigated and characterized. By directly measuring the substrate current from conventional TFTs with body contact, the impact-ionization effects can be characterized and analyzed very clearly. An anomalous substrate current under high gate voltage is observed. The parasitic tunneling effect between inversion region and body region is proposed to explain this phenomenon. Finally, a physically-based model is established and compared with the measured substrate current. Good agreements are found when the vertical field scattering effect is included into the maximum electric field impact ionization model.

The purpose of this study is using titanium dioxide (TiO2) as gate oxide on thin film transistor (TFT) and discussed with their physical, chemical and electrical properties. Amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) are used as substrates. The metal-organic chemical vapor deposition (MOCVD) and the liquid phase deposition (LPD) are used as the TiO2 growth methods. About the LPD growth method, ammonium hexafluoro-titanate ((NH4)2TiF6) and hexafluorotitanic acid (H2TiF6) are used as Ti sources. We are interested in two parts: (1) the growth mechanisms, physics properties, chemical properties and electrical properties of MOS structure; (2) the fabrication processes and electrical properties of devices. In the first part, we discuss the thin films characteristics on a-Si and poly-Si substrates. For the MOCVD growth method, the MOCVD-TiO2 film tends to form the poly structure. Poly structure has a higher dielectric constant, however, higher traps and dangling bonds also exist at the grain boundaries. Thus, poly structure of TiO2 film has a higher leakage current. For the LPD growth method, the film tends to form the amorphous structure. Amorphous structure has lower leakage current but also has lower dielectric constant. The film that grown from the (NH)2TiF6 source is called LPD-TiO2 film. The film that grown from the (NH)2TiF6 source is called LPD-TixSi(1-x)Oy film. Both films are incorporated with OH and F ions during the growth, the OH and F ions can be outgassed during the low temperature annealing process. In addition, appropriate F ions in the film can passivate the traps and dangling bonds. The low temperature treatments in N2 or O2 ambient and post-metallization annealing (PMA) are adopted to improve the film characteristics. On the other hand, the substrate is not a prefect structure (not a single structure). Thus the film may be influenced by substrate during the annealing treatment. In the second part, the electrical properties of TFT devices were discussed under the coplanar structure. There are several differences of the operation principle in TFT and MOSFET. A-Si and poly-Si are the un-doped substrates with many traps in the bulk. The channel should be occurred through the full depletion mode. The full depletion region is the substrate that under the gate electrode. Thus, the key point is kept the suitable thickness. Too thick, the channel can not appear. Too thin, the substrate may be over-etched. For ion implantation, due to the thinner active layer, the ion implantation energy should be lowed. In addition, the activation temperature and activation time should be adjusted suitable. We have fabricated the TFT devices with the MOCVD-TiO2 as gate oxide on poly-Si substrate. From the I-V characteristics, the Kink effect can be observed. However, the Ion/Ioff ratio is still low. We must further study how to increase the Ion/Ioff ratio.

The study of impurity diffusion in semiconductor hosts is an important field that has both fundamental appeal and practical applications. Ion implantation is a good technique to introduce impurities deep into the semiconductor substrates at relatively low temperature and is not limited by the solubility of the dopants in the host. However ion implantation creates defects and damages to the substrate. Annealing process was used to heal these damages and to activate the dopants. In this study, we introduced several species such as alkali metals (Li, Na, K), alkali earth metals (Be, Ca,), transition metals (Ti, V, Cr, Mn) and other metals (Ga, Ge) into semiconductor substrates using ion implantation. The implantation energy varies form 70 keV to 200 keV and the dosages vary between ~ 1.0x1012 and ~5.0x1015 atoms/cm2. The samples are annealed at different temperatures from 300°C to 1000°C and for different time intervals. The redistribution behaviors of the implanted ions are studied experimentally using secondary ion mass spectrometry (SIMS). We observed some complex distribution behaviors due to the defects created during the process of ion implantation. The diffusivities of some impurities are calculated and compared to previous data. It was found that the diffusivities of implanted impurities is related to the dosages, annealing temperatures and the defects and damages caused by ion implantation. Additionally, as we go from one type of semiconductor to another, the diffusion behavior of the impurities shows a different trend.

Dans le contexte des cellules photovoltaïques (PV) à base de silicium cristallin (c-Si), le développement de structures de contacts dits « passivants », qui permettent de limiter les pertes par recombinaisons des porteurs de charge à l’interface entre le métal et le c-Si, est un des principaux leviers vers l’obtention de plus hauts rendements. Une approche de contacts passivés consiste à intégrer entre le métal et le c-Si une jonction composée d’une couche de silicium poly-cristallin (poly-Si) fortement dopée sur une mince couche d’oxyde de silicium (SiOx < 2 nm).Les objectifs de ce travail sont d’une part de développer une jonction poly-Si/SiOx compatible avec la fabrication industrielle des cellules PV, et d’autre part d’améliorer la compréhension des mécanismes de passivation et de transport des charges au niveau de la fine couche de SiOx située à l’interface entre le poly-Si et le c-Si.Dans ce travail, une jonction de poly-Si/SiOx dopée au bore a été développée, le dopage de la couche étant dans un premier temps réalisé in-situ pendant l’étape de dépôt chimique en phase vapeur assisté par plasma (PECVD) de la couche poly-Si. La méthode de dépôt PECVD est répandue dans l’industrie PV et permet la fabrication de la couche poly-Si d’un seul côté du substrat c-Si. Cependant, elle induit une forte concentration d’hydrogène dans la couche déposée, ce qui entraine la formation de cloques à l’interface avec le c-Si et tend à dégrader les propriétés de passivation de surface de la jonction après recuit de cristallisation. L’optimisation des conditions de dépôt (température de dépôt et ratio de gaz H2/SiH4) a permis d’obtenir des couches de poly-Si dopées in-situ intègres. Par la suite, une méthode de dopage alternative, par le biais du dépôt d’une couche diélectrique riche en bore sur le poly-Si, a été appliquée afin de réduire l’apport en hydrogène pendant le dépôt et d’obtenir des couches de poly-Si intègres plus épaisses. L’ajout d’une étape d’hydrogénation a permis d’obtenir des propriétés de passivation de surface au niveau de l’état de l’art pour les deux types de jonctions poly-Si/SiOx développées.A la suite du développement de la jonction poly-Si/SiOx, la caractérisation physico-chimique de la couche SiOx a été réalisée et a démontré une possible amélioration de la stœchiométrie de la couche vers SiO2 ainsi qu’une dégradation de son homogénéité en épaisseur sous l’effet du recuit de cristallisation à haute température. Ces phénomènes pourraient s’expliquer par une diffusion des atomes d’oxygène à l’interface. D’autre part, l’étude du transport des charges à travers le SiOx par C-AFM a mis en évidence les limites de cette technique quant à la détermination de nano-ouvertures au sein de la couche SiOx (qui favoriseraient le transport des charges). Enfin, une méthode de caractérisation des défauts recombinants à l’interface entre une jonction de poly-Si intrinsèque et le c-Si a été mise en œuvre. Cette méthode a permis de modéliser les recombinaisons à l’interface poly-Si/c-Si via deux défauts discrets apparents dont les niveaux d’énergie dans la bande interdite et les ratios de sections efficaces de capture des électrons et des trous ont été déterminés. / In the context of high efficiency solar cells (SCs) based on crystalline silicon (c-Si), the development of "passivating" contact structures to limit the recombination of charge carriers at the interface between the metal electrode and the c-Si has been identified as the next step to further improve the photovoltaic (PV) conversion efficiency. Passivating contacts consisting of a highly doped poly-crystalline silicon layer (poly-Si) on top of a thin layer of silicon oxide (SiOx ≤ 2 nm) are particularly sparking interest as they already demonstrated promising conversion efficiency when integrated in SCs.The objectives of this work are to develop a poly-Si/SiOx passivating contact compatible with the industrial production of c-Si SCs, and to investigate the passivation and charge transport mechanisms in the region of the thin SiOx layer located at the interface between the poly-Si and the c-Si.In this work, a boron-doped poly-Si/SiOx contact was fabricated. The doping of the layer was first performed in-situ during the deposition of a hydrogen-rich amorphous silicon (a-Si:H) layer by plasma-enhanced chemical vapor deposition (PECVD). The PECVD step was followed by an annealing step for crystallization of the poly-Si layer. The PECVD presents the advantages of being widespread in the PV industry and enabling the fabrication of the poly-Si contact on a single side of the c-Si substrate. However, it induces a high concentration of hydrogen in the deposited layer, which causes the formation of blisters at the interface with the c-Si and tends to degrade the surface passivation properties of the contact after annealing for crystallization. The optimization of the deposition conditions (temperature and H2/SiH4 gas ratio) enabled to obtain blister-free in-situ doped poly Si layers. An alternative doping method consisting of the deposition of a boron-rich dielectric layer on top of the poly-Si layer was applied to reduce the hydrogen content of the deposited layer. This approach enabled to obtain thicker blister-free poly-Si layers. The diffusion of hydrogen in the contact after annealing is known to provide a further chemical passivation of the poly-Si/c-Si interface. In this work, the addition of a hydrogenation step enabled to obtain state-of-the-art surface passivation properties for the two types of poly Si/SiOx contact fabricated.After developing the poly-Si/SiOx contact, a study of the effect of the annealing step on the chemical and structural properties of the SiOx layer was performed. Results indicated a possible improvement of the stoichiometry of the layer towards SiO2 as well as a degradation of its homogeneity at the poly-Si/c-Si interface after annealing at high temperature. These phenomena could be explained by a diffusion of the oxygen atoms content in the interfacial SiOx layer. The transport mechanism of charge carriers through the SiOx layer was conducted by C-AFM. This study revealed the limits of this technique to determine the presence of pinholes within the SiOx layer (that would help the transport of charge carriers). Finally, a method for characterizing recombinant defects at the interface between an intrinsic poly-Si junction and the c-Si has been developed. This method enabled to model the recombination phenomena at the poly-Si/c-Si interface via two apparent discrete defects. Their associated energy levels in the bandgap and ratios of electron and hole capture cross sections were estimated.

¡@¡@Because of the poly-si thin film transistor have the advantage of high mobility, it can improve the analysis for the flat plan display. Using the above advantage can combine the integrated circuit as control IC and memory on the small panel to reduce the number between the switch circuits and the outside contacts. These precise circuits must be considering the photo current¡Bthermal effects and the parasitical capacitance more due to the influence of these precise circuits is more serious than the switch circuits. In my thesis, the research of the electrical characteristics of the newest excimer laser crystallize coplane poly-si thin film transistors ,and using the device length with width is 128um/6um and 128um/16um can be extracted that the environment of the facing illumination have the photo-leakage current than none illumination about four orders, and the photo-leakage current is not consider with any gate voltage. ¡@¡@With the discussion of the capacitance, the main point of my researches is to change different conditions to extract the gate to source capacitance (Cgs). In addition, the slight carriers may effect the devices with the high mobility system on panel (SOP) technology error, the temperature must be considered. ¡@¡@We find the mobility is bigger at the environment of the temperature is 300K than the environment of the temperature is 100K when the device work in the linear region and the on current is lower at the environment of the temperature is 300K than the environment of the temperature is 100K when the device work in the saturation region. Using some references and some models as the concepts can analysis some phenomenons I refer to above.

When the size of display panel increased, the RC delay of TFTs became serious. High dielectric (high-k) materials used as the gate oxide can increase the gate oxide capacitance Co, which can induce a higher drain current, and higher aperture ratio. Therefore, low-k materials are used for inter-metal dielectrics. Thus, it can improve the RC delay. LPD-TiO2 film on a-Si and poly-Si technology and characterization of films were described in detail in this thesis. The highest dielectric constant of 11.76 and 29.54, and lowest leakage current density of 5.45¡Ñ10-7A/cm2 at -0.45 MV/cm and 3.11¡Ñ10-1 A/cm2 at 0.45 MV/cm for the O2-annealed of LPD-TiO2film on a-Si and poly-Si can be obtained.