International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper introduces the development of an S-band miniaturized solid-state pulse transmitter. Four-way power combination technique is applied to raise output power. The output power of the RF pulse exceeds 500W, and the combined efficiency amounts to 90%. The transmitter has many other good characteristics, such as small dimensions, light weight, low power consumption, high duty factor and so on. Development of this transmitter will greatly improve the ability of telemetry. It will undoubtedly promote the application and development of pulse telemetry system.

Abstract Recently, the proliferating needs of high data rate communication systems are increasing the demand for higher frequency bands with broader bandwidth. The K-band (18~26.5 GHz), which include point to point communications (18~23 GHz), ISM band (24 GHz), and automotive radar applications (24 GHz and 22~29 GHz) is one of the most important frequency bands in modern wireless communication systems. This thesis mainly includes three parts. The first part of the thesis is the introduction to the principles and characteristics for active and passive components of CMOS process and the description of common transistors , such as BJT, CMOSFET, HBT and pHEMT. The principles of resistors, capacitors and inductors in simulations is shown. It is useful for the microwave circuit design to understand the structure and characteristics of active components and passive components in CMOS process. The second part describes the design principles and characteristics of power amplifier. The third part is the design and simulation of the 2 stages cascode configuration Class A power amplifier and the 3 stages cascode configuration Class A power amplifier with power combination. There are two important scaling trends that are making CMOS increasingly attractive for RF applications. One is the well known dramatic shrinkage of device size, so that transistors in the advanced process generation of CMOS have peak fT values in excess of 55 GHz.The other is the reverse scaling of interconnect. The thicker metal layer and more layers of wiring are enabling the realization of high-quality passive components which are critical for RF circuits. CMOS is the most attractive technology for its low cost, high yield and high level of integration. However, It is challenging to design a power amplifier with high output power. In the sub-micron CMOS technology, the challenges of CMOS power amplifier design include the low breakdown voltage, low transconductance (gm), and high substrate loss as compared with SiGe HBTs GaAs HBTs and InP-GaAs HBTs technologies. We made efforts in implementing a power amplifier at K-band. The design and simulation of two power amplifier is present. One is the 2 stages power amplifier, the other is the 3 stages power amplifier with power combination. In order to realize the inductive element and capacitive element in sub-milimeter wave or millimeter wave circuit design, the short stub microstrip line and open stub mircrostrip line are used in matching networks between all stages. The cascade configuration is effective structure to minimize Miller effect in high frequency. The peak gain of 2 stages power amplifier is 17 dB at 24 GHz and the saturation output power is 20 dBm. The OP1dB is over 16 dBm. The peak gain of 3 stages power amplifier with power combination is 20 dB at 24 GHz and the saturation output power is 20.5 dBm. The OP1dB is over 15 dBm.The power amplifier with the cascode configuration and power combination techniques is designed and simulated in TSMC 0.18 um CMOS process, which provides deep n-well, and MiM capacitors.