Abstract Recently, the proliferating needs of high data rate communication systems are increasing the demand for higher frequency bands with broader bandwidth. The K-band (18~26.5 GHz), which include point to point communications (18~23 GHz), ISM band (24 GHz), and automotive radar applications (24 GHz and 22~29 GHz) is one of the most important frequency bands in modern wireless communication systems. This thesis mainly includes three parts. The first part of the thesis is the introduction to the principles and characteristics for active and passive components of CMOS process and the description of common transistors , such as BJT, CMOSFET, HBT and pHEMT. The principles of resistors, capacitors and inductors in simulations is shown. It is useful for the microwave circuit design to understand the structure and characteristics of active components and passive components in CMOS process. The second part describes the design principles and characteristics of power amplifier. The third part is the design and simulation of the 2 stages cascode configuration Class A power amplifier and the 3 stages cascode configuration Class A power amplifier with power combination. There are two important scaling trends that are making CMOS increasingly attractive for RF applications. One is the well known dramatic shrinkage of device size, so that transistors in the advanced process generation of CMOS have peak fT values in excess of 55 GHz.The other is the reverse scaling of interconnect. The thicker metal layer and more layers of wiring are enabling the realization of high-quality passive components which are critical for RF circuits. CMOS is the most attractive technology for its low cost, high yield and high level of integration. However, It is challenging to design a power amplifier with high output power. In the sub-micron CMOS technology, the challenges of CMOS power amplifier design include the low breakdown voltage, low transconductance (gm), and high substrate loss as compared with SiGe HBTs GaAs HBTs and InP-GaAs HBTs technologies. We made efforts in implementing a power amplifier at K-band. The design and simulation of two power amplifier is present. One is the 2 stages power amplifier, the other is the 3 stages power amplifier with power combination. In order to realize the inductive element and capacitive element in sub-milimeter wave or millimeter wave circuit design, the short stub microstrip line and open stub mircrostrip line are used in matching networks between all stages. The cascade configuration is effective structure to minimize Miller effect in high frequency. The peak gain of 2 stages power amplifier is 17 dB at 24 GHz and the saturation output power is 20 dBm. The OP1dB is over 16 dBm. The peak gain of 3 stages power amplifier with power combination is 20 dB at 24 GHz and the saturation output power is 20.5 dBm. The OP1dB is over 15 dBm.The power amplifier with the cascode configuration and power combination techniques is designed and simulated in TSMC 0.18 um CMOS process, which provides deep n-well, and MiM capacitors.

Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés. / For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.