Broadband over Power Line (BPL) technology has garnered significant attention lately due to recent advancements in solid state technologies and channel coding schemes. The successful application of BPL technology for in-home automation and networking has led to suggestions of applying BPL in other systems including ships. The application of BPL technology using the Shipboard Power System (SPS) as a potential communications network for ship automation systems has been proposed, to achieve recent U.S. Navy ship management concepts geared toward reducing ship manning while improving operational efficiency. This thesis presents an analytical model developed to examine the channel response characteristics and estimated throughput capacity of SPS cables. The work used a multiconductor transmission line theory based approach to model the channel response of SPS distribution lines and estimated the channel throughput capacity using a “water-filling” communication technique. This work found that BPL using the SPS holds a strong potential for use as a communications network for ship communication systems.

Broadband over Power Line (BPL) technology has garnered significant attention lately due to recent advancements in solid state technologies and channel coding schemes. The successful application of BPL technology for in-home automation and networking has led to suggestions of applying BPL in other systems including ships. The application of BPL technology using the Shipboard Power System (SPS) as a potential communications network for ship automation systems has been proposed, to achieve recent U.S. Navy ship management concepts geared toward reducing ship manning while improving operational efficiency. This thesis presents an analytical model developed to examine the channel response characteristics and estimated throughput capacity of SPS cables. The work used a multiconductor transmission line theory based approach to model the channel response of SPS distribution lines and estimated the channel throughput capacity using a “water-filling” communication technique. This work found that BPL using the SPS holds a strong potential for use as a communications network for ship communication systems.

ITC/USA 2015 Conference Proceedings / The Fifty-First Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2015 / Bally's Hotel & Convention Center, Las Vegas, NV / Power line communications (PLC)-based transceivers provide an alternative to establishing dedicated aircraft Ethernet networks. Adding new aircraft functionality or installing special purpose instrumentation often requires significant engineering and aircraft down time to complete. PLC-based networks can reduce project cost and schedule by enabling localized aircraft modifications and leveraging existing aircraft wiring for the Ethernet medium. PLC standards continue to evolve and achieve greater throughput rates and noise mitigation. Ethernet communications have been tested over AC and DC power busses, data busses, and discrete wiring. PLC networks have been successfully demonstrated in avionics test beds and aircraft (including live video transfers) without causing interference to the basic systems or the underlying wiring functionality. PLC transceivers provide a cost effective solution to the adding Ethernet capabilities or Ethernet-based subsystems to existing aircraft.

Σκοπός της εργασίας αυτής είναι να εξετασθεί πως μπορεί να πραγματοποιηθεί η μεταφορά δεδομένων μέσω των γραμμών ρεύματος, ποιοι είναι οι ανασταλτικοί παράγοντες σε αυτή τη διαδικασία, με ποιους τρόπους μπορεί να εξασφαλίσουμε όσο το δυνατόν λιγότερα σφάλματα και πως μπορεί να υλοποιηθεί αυτό στην πράξη. Για τα παραπάνω θα γίνουν προσομοιώσεις με βάση πειραματικά δεδομένα που έχουν δημοσιευτεί, αλλά όχι δικά μας πειράματα σε πραγματικές γραμμές. Λόγω της χαμηλής ποιότητας της μεταφοράς αυτής προτείνεται και μια μέθοδος η οποία προσαρμόζεται στις συνθήκες του εκάστοτε καναλιού και ελαχιστοποιεί τα προβλήματα αυτού. Αρχικά αναλύονται και περιγράφονται τα διάφορα μοντέλα που έχουν προταθεί για την περιγραφή ενός συστήματος PLC. Στη συνέχεια, εξετάζεται ο τρόπος μετάδοσης που θα χρησιμοποιηθεί, δηλαδή τα OFDM, καθώς και διάφορες κωδικοποιήσεις και διαμορφώσεις που χρησιμοποιούνται. Κατόπιν, με χρήση των δύο παραπάνω, δηλαδή του μοντέλου του καναλιού και του τρόπου μετάδοσης, προχωράμε σε μια προσομοίωση του όλου συστήματος για να εξετάσουμε τα πιθανά σφάλματα και να κάνουμε τις απαραίτητες βελτιώσεις. Στις προσομοιώσεις αυτές θέλουμε να υπάρχουν λίγα σφάλματα αλλά υψηλή ταχύτητα μετάδοσης. Τα αποτελέσματα των προσομοιώσεων αυτών δεν είναι ικανοποιητικά για εμάς, οπότε προτείνουμε έναν τρόπο βελτίωσης του τελικού αποτελέσματος, ο οποίος βασίζεται στην αναγνώριση του καναλιού από το οποίο γίνεται η μετάδοση ώστε να μηδενιστεί το σφάλμα. Με χρήση αυτής της αναγνώρισης του καναλιού, έχουμε πολύ καλά αποτελέσματα, αφού μόνο σε περιπτώσεις πολύ υψηλού θορύβου έχουμε μεγάλο σφάλμα. Όταν ο θόρυβος πέφτει σε φυσιολογικά επίπεδα τότε το σφάλμα είναι σχεδόν μηδενικό, όποτε μπορεί να θεωρηθεί ότι η μετάδοση γίνεται σωστά. Τελικά προσομοιώνουμε ένα σύστημα το οποίο μεταδίδει στο φάσμα 5-15MHz ενώ τα δεδομένα μας αποστέλλονται με ταχύτητα 64Mbps. / The purpose of this project is to test the power line channel as a communication channel. We test deifferent models of the channel and simulate the data transfer. Finally we get good results as we use a channel estimation to improve the transfer quality. The tranfer is at the band of 5-15MHz, with 64Mbps.

Power line communications (PLC) has been considered by utility companies for over a half century and for home networking in recent years. However, PLC at the IC level, or even at the PCB level, has not been investigated outside Dr. Ha's research group. This thesis investigates the feasibility of PLC over power distribution networks (PDNs) of advanced microprocessors. A PDN in an integrated circuit (IC) is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple sensing/control circuit to the node. Routing the data through a power line avoids the necessity of preplanning the routing of a data path between the node and an external data pin. PLC over microprocessor PDNs also provide a viable means for "run-time testing" as well as for monitoring the so called "large time-constant errors" resulting from aging and temperature variations. In this thesis, we considered impulse-based ultra wideband (I-UWB) communication technology for PLC over PDNs of microprocessors. I-UWB has several advantages for PLC over PDNs due to its robustness to multipath effects, simple hardware for transmission and reception of pulses and, more importantly, reduced interference to the normal operation of microprocessors. A microprocessor PDN is heavily decoupled to damp the resonances in the power supply impedance as well as to reduce the slew rate of current variations by locally supplying (sinking) currents to (from) the switching nodes. Consequently, a PDN behaves like a bulky lowpass filter for high frequency signals. However, the inductance component of decoupling capacitors becomes more significant beyond the self resonant frequency (SRF) of the capacitors. So, a PDN becomes essentially a distributed circuit beyond the SRF and is no longer a lowpass filter. Indeed, high frequency PDN models developed earlier at Dr. Ha's group show that there exist multiple frequency bands where high frequency signals can propagate through the PDN with relatively low attenuation [3] [4]. The major contributions of our research lie in three areas. First, we verified existence of passbands on PDN's transfer characteristics through measurements. We carried out high frequency measurements on the PDN of Intel's 65 nm Pentium processor and 45 nm Core 2 Duo processor. We measured PDN transfer characteristics up to several GHz from a core power pin on a tester board to an on-chip power node for both active and cold microprocessor dies. The measurements show the existence of narrow, sporadic and migratory passbands i.e. location of passbands change from one generation of processor to the next. The migratory nature of passbands requires the I-UWB receiver and a transmitter to cover a wide range of frequencies rather than a specific passband. Second, we have developed a PDN communication channel model for system level study. To develop the channel model, we also performed noise measurements on Intel microprocessors. The link budget was calculated based on the channel model and appropriate modulation schemes were suggested through the system level study. Third, we investigated design of an I-UWB receiver and a transmitter, which cover a wide bandwidth. The proposed receiver and transmitter designs were evaluated through simulations in TSMC 0.18 μm CMOS process. Our simulation indicates that the PLC over a PDN is feasible with a relatively simple digital-process friendly I-UWB receiver and a transmitter. / Ph. D.

This thesis investigates a new data communication method in high speed integrated circuits using power distribution networks (PDNs). The conventional purpose of PDNs in integrated circuits (ICs) is to deliver power to internal nodes of an IC while meeting a level of power integrity. As the power consumption increases for very large scale integration (VLSI) systems, the number of power/ground pins increases as well. In this thesis, we propose to use PDNs for dual purposes, delivery of power and one-/two-way data communications, which is highly beneficial for pin-limited high performance ICs. To this end, we investigate signaling methods for a microscopic communication channel. Impulse-based ultra wideband (UWB) signaling is selected due to its robustness to noise and wideband characteristics. Next, we study a planar structure IC package based on the cavity resonator model (CRM) as a communication channel. Impedance characteristics of a planar structure IC package and other relevant components of an IC are important, and they are investigated for data transmission over power distribution networks. Another important aspect of the study is data transmission and reception, which we investigate through simulations. Finally, we study one possible application for one way communications, massive parallel scan design, which greatly shortens the testing time at moderate overhead. The performance is measured with eye diagrams and bit error rates (BERs) under the presence of voltage drop, simultaneous switching noise, and thermal noise. / Ph. D.

Power line communications (PLC) in integrated circuits (ICs) was proposed by Dr. Dong S. Ha's group in 2005. Their goal was to utilize the power distribution network for data communications as well as delivery of power, so that the routing overhead can be avoided and the number of pins in the chip can be reduced. Dr. Ha's group demonstrated through measurements the existence of pass-bands in the power distribution networks and the feasibility of power line communications in ICs. Several PLC receivers were developed to recover data superimposed on the power lines of an IC. This thesis research investigated a new PLC receiver to improve shortcomings of previous PLC receivers, specifically to improve the reliability while reducing power dissipation. The proposed PLC system adopts an amplitude shift keying (ASK) modulation to transmit and detect data through power distribution networks. The proposed PLC receiver consists of three main sub-blocks. The first sub-block is a level shifter, which lowers the offset voltage of the supply voltage to approximately 0.5VDD. The second sub-block is a signal extractor, which detects a data signal superimposed on the power line. The signal extractor is a differential amplifier, in which one input is connected through an RC low-pass filter. The DC voltage of the data signal varies in accordance with the supply voltage fluctuations and droop. The low-pass filter intends to pass only the DC term of the data signal. Since the DC voltage is common for both inputs of the differential amplifier, it is removed from the data signal through the common mode rejection of the differential amplifier. Therefore, the signal extractor can mitigate supply voltage fluctuations and droops. The last sub-block is the logic restorer, which converts the differential signal to a logic value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improves the noise immunity of the receiver The proposed PLC receiver is designed and fabricated in CMOS 0.18 µm technology under the supply voltage of 1.8 V. Measurement results of the three sub-blocks and the entire PLC receiver are presented and compared with simulation results. The data rate for the measurements is set to 10.0 Mbps, and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core area of the receiver is 72.2 µm x 74.9 µm. / Master of Science

Power line communications (PLC) as applied to electrical power grid is known since long; however, PLC in microprocessors was recently introduced by VTVT Lab. Since power distribution network (PDN) inside a microprocessor is ubiquitous, therefore, any node inside a microprocessor can be accessed by attaching a simple communication circuit to it. The scheme is extremely attractive as it avoids the routing overhead of the data-path between an internal node and an I/O pin. A number of applications are possible for PLC in microprocessors such as on-line testing, monitoring/control of internal nodes, fault diagnosis etc. Feasibility of the PLC approach has been extensively studied by earlier researchers at VTVT. The feasibility studies investigated the frequency response of a microprocessor's PDN and looked for existence of passbands — frequency bands where signal attenuation through the PDN is small. Two different approaches were followed—the first approach employed analytical modeling of the high frequency characteristics of the PDN, while the second approach conducted measurements on Intel® microprocessors' PDN. Although, differences were observed in the results of the two approaches; both the approaches demonstrated existence of passbands, thus affirming the feasibility of the PLC scheme. This thesis presents a system level study conducted to estimate performance of the PLC scheme. Measurement results were used to model the PDN channel. The study provides useful insights for the design of microprocessor level PLC system. Specifically, the study estimates optimal pulse width required to maximize the system performance and the range of achievable data-rates. The study demonstrates that it is feasible to communicate data through a microprocessor's PDN without inducing large disturbances on the power line. The other work presented in this thesis is the design of low power receiver for microprocessor level PLC, also called data recovery block. The proposed design of data recovery block employs Correlation Detection (CD) receiver architecture. The design has been implemented in IBM 0.13 µm CMOS process and has been verified to operate reliably across Process, Voltage and Temperature variations. The design has a small foot-print of 300 µm x 160 µm and consumes 3.58 mW while operating from 1.2 V power supply. / Master of Science

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / This paper introduces a study of the feasibility and initial hardware design for transmitting data over aircraft power lines. The intent of this design is to significantly reduce the wiring in the aircraft instrumentation system. The potential usages of this technology include Common Airborne Instrumentation System (CAIS) or clock distribution. Aircraft power lines channel characteristics are presented and Orthogonal Frequency Division Multiplexing (OFDM) is introduced as an attractive modulation scheme for high-speed power line transmission. A design of a full-duplex transceiver with accurate frequency planning is then discussed. A general discussion of what communications protocols are appropriate for this technology is also provided.

A presente dissertação tem como objetivo principal a validação do modelo matemá- tico PI a partir da avaliação do seu desempenho tanto a nível de representação elétrica, como também nas transmissões de sinal de comunicação em alta frequência, usualmente utilizadas em tráfego conhecido como Power Line Communication (PLC). Para atingir este objetivo, inicialmente, foi realizado o estudo e avaliação dos modelos matemáticos utilizados para representar um segmento de distribuição de energia. Depois foi utilizado um emulador em escala de potência reduzida, validado para baixa frequência, objetivando avaliar o modelo matemático escolhido. Como o foco do trabalho é a rede de distribuição em baixa tensão, foi realizada a construção de um circuito elétrico representativo de um trecho real de uma concessionária de energia, no caso deste trabalho o DEMEI, que foi implementado computacionalmente utilizando a ferramenta matemática Matlab e sicamente em um dos laboratórios do Grupo de Automação Industrial e Controle (GAIC). Foi realizado um conjunto signi cativo de medições, de corrente e tensão, no circuito real e os resultados foram comparados com os dados obtidos a partir das simulações computacionais do modelo escolhido para representar o circuito real utilizando uma transmissão PLC, no caso o modelo PI. A partir da análise dos resultados reais com os obtidos das simulações computacionais foi possível comprovar que o modelo PI representa satisfatoriamente o trecho simulado em relação a transmissão em altas frequências, uma vez que o sinal PLC transmitido no trecho simulado no Matlab em relação ao trecho real teve um erro inferior a 1%. / 128 f.