<p>As technological advances enable computers to permeate many of our society's critical application domains (such as medicine, finances, transportation), the requirement for computers to always behave correctly becomes critical as well. Currently, ensuring that processor designs are correct represents a major challenge for the computing industry consuming the majority (up to 70%) of the resources allocated for the creation of a new processor. Looking towards the future, we see that with each new processor generation, even more transistors fit on the same chip area and more complex designs become possible, which makes it unlikely that the difficulty of the design verification problem will decrease by itself.</p><p>We believe that the difficulty of the design verification problem is compounded by the current processor design flow. In most design cycles, a design's verifiability is not explicitly considered at an early stage - when decisions are most influential - because that initial focus is exclusively on improving the design on more traditional metrics like performance, power, and area. It is thus possible for the resulting design to be very difficult to verify in the end, specifically because its verifiability was not ranked high on the priority list in the beginning. </p><p>In this thesis we propose to view verifiability as a critical design constraint to be considered, together with other established metrics, like performance and power, from the initial stages of design. Our high level goal is for this approach to make designs more verifiable, which would both decrease the resources invested in the verification step and lead to more robust designs. </p><p>More specifically, we make five main contributions in this thesis. The first is our proposal for a change in design perspective towards considering verifiability as a first class constraint. Second, we use formal verification (through a combination of theorem proving, model checking, and probabilistic model checking ) to quantitatively evaluate the impact on verifiability of various design choices like the organization of caches, TLBs, pipeline, operand bypass network, and dynamic power management mechanisms. Our third contribution is to evaluate design trade-offs between verifiability and other established metrics, like performance and power, in the context of multi-core dynamic power management schemes. Fourth, we re-design several components for increasing their verifiability. Finally, we propose design guidelines for increasing verifiability. In the context of single core processors our guidelines refer to the organization of caches and translation lookaside buffers (TLBs), the depth of the core's pipeline, the type of ALUs used, while for multi-core processors we refer to dynamic power management schemes (DPMs) for power capping. </p><p>Our results confirm that making design choices with verifiability as a first class design constraint has the capacity to decrease the verification effort. Furthermore, making explicit trade-offs between verifiability, performance and power helps identify better design points for given verification, performance, and power goals.</p> / Dissertation

The purpose of this paper is to design a laser scanning system for a high temperature and acidic environment to measure small-scale surface roughness of seabed and to collect information related to calcium carbonate debris. The study comprises two parts. One is to construct the hardware and software of the laser scanning system. Two is to test the system at sea. The system were tested at Kuishantao sea area, an area with many submarine springs. The temperature of the hot water from the submarine springs can be as high as 126¢XC. Key substances from this type of hot springs are surfur and air bubbles composed of CO2, N2, O2, SO2, and H2S. These chemicals make the sea water in this area acidic, and the pH value can be less than 2. In other words, this sea area is a high temperature and very acidic environment According the acidic resistant test result, the researchers decided to use Polypropylene (PP) as the material. The laser scanning system captures information automatically, and it uses industrial single board computer (PC104) as the control platform. The researchers selected red laser, which is monotonous, directional, and coherent Lithium batteries, can be recharged repetitively, were used to supply the power. High-precision positioning, high resolution, and with easy speed and angle control stepping motors were chosen for the system. For the software, the researchers chose the Window operating system. The hardware and software of this system are highly compatible. Operating the system is very intuitive because windows are used as the interface, and the hardware has high supporting capacity. This arrangement makes data analysis later on very convenient. Images acquired from conducting the actual experiment at sea that need to be processed. A CCD camcorder with fixed location and angle was used to capture images. With the high brightness characteristic of laser and simple threshold values for screening, the researchers got the pixel position of laser beans. Then a calibrated the camcorder was used to switch the pixel coordinates to obtain the actual size of the object.

The switched reluctance motor has the advantages of the low production cost, high operating efficiency, high stability, and high start torque. It can deliver a wide speed range, and therefore make it very attractive to the engineers and researchers. The double salient structure of SRM result in a non-linear stator inductance, so the output reluctance torque has a highly non-linear behavior. A digital signal processor based drive system for SRM is developed and implemented in this thesis using the TI TMS320F240 DSP system which is with universal peripheral interface circuits. The built-in pulse width modulation(PWM) module of the DSP system can auto-generate PWM output signal by setting the relative registers to simplify the hardware design. This research built a complete drive system for SRM, both the closed-loop velocity controller and current compensator were designed according to the proportional-integral(PI) control mechanism, and all schemes were coded in the DSP program. Simulation and experiment results demonstrate that the proposed drive system makes reluctance torque output very smoothly with a preferable velocity response.

In this thesis, an FPGA based hash processor is designed and implemented using a hardware description language / VHDL. Hash functions are among the most important cryptographic primitives and used in the several fields of communication integrity and signature authentication. These functions are used to obtain a fixed-size fingerprint or hash value of an arbitrary long message. The hash functions SHA-1 and SHA2-256 are examined in order to find the common instructions to implement them using same hardware blocks on the FPGA. As a result of this study, a hash processor supporting SHA-1 and SHA2-256 hashing and having a standard UART serial interface is proposed. The proposed hash processor has 14 instructions. Among these instructions, 6 of them are special instructions developed for SHA-1 and SHA-256 hash functions. The address length of the instructions is six bits. The data length is 32 bits. The proposed instruction set can be extended for other hash algorithms and they can be implemented over the same architecture. The hardware is described in VHDL and verified on Xilinx FPGAs. The advantages and open issues of implementing hash functions using a processor structure are also discussed.

Abstract The tremendous progress in all aspects of signal processing technology has naturally been accompanied by a corresponding development of arithmetic techniques to provide high-speed operations at reasonable complexity. In the past, many architectural design efforts have focused on maximizing performance for frequently executed simple arithmetic operations such as addition and multiplication while left other rarely used operations ignored. In this dissertation, we firstly propose two design approaches for 64-b carry-lookahead adders (CLA) using a two-phase clocking dynamic CMOS logic since fast adders are the key elements in many digital circuits. Secondly, we place emphasis on the inner product operation since it is one of the most frequently used mathematical operations in the computation of digital neural networks. A ratioed 3-2 compressor is also presented to resolve several physical design problems that are not fully considered or implemented in previous research works. Finally we propose several fast 64b/32b integer dividers because the integer division is unavoidable in many important signal-processing applications.

This paper design a Digital-Singal-Processor based which cooperating with the technique of switching power supply to implement the Brushless DC motor driver for electric vehicle ,and use the asymmetry pulse-width modulation theorem in sinusoidal PWM switch to increase motion efficiency of motor and decrease the power depletion ,thus can improve the current- spike from analog controller effectively ,and prove the feasibility of the system.

This paper designs and implements a DSP based intelligent battery charger and residual capacity estimator for electric vehicle. This system uses the proposed new electric circuit structure and the intelligent fuzzy charge algorithm to charge batteries, and the improved coulometric measurement with accurate residual capacity estimation to estimate the residual capacity of batteries. From the experimental results, the charger can achieve the purpose of fast and uniform charge with charging time six (6) to eight (8) hours, and will not cause the damage of battery because of using the intelligent fuzzy charge algorithm can give different charging current depend on the difference of voltage, capacity and temperature of battery; the residual capacity estimator can accurate estimate the residual capacity of batteries due to calculating the increment current and considering the aging factor.

This paper Management and Diagnosis a DSP based intelligent battery charger and residual capacity estimator for electric vehicle. This system uses the proposed new electric circuit structure and the intelligent fuzzy charge algorithm to charge batteries, and the improved coulometric measurement with accurate residual capacity estimation to estimate the residual capacity of batteries. From the experimental results, the charger can achieve the purpose of fast and uniform charge with charging time six (6) to eight (8) hours, and will not cause the damage of battery because of using the intelligent fuzzy charge algorithm can give different charging current depend on the difference of voltage, capacity and temperature of battery; the residual capacity estimator can accurate estimate the residual capacity of batteries due to calculating the increment current and considering the aging factor.

This paper designs and implements a DSP based intelligent battery charger and residual capacity estimator. This system uses the proposed structure of the series circuit and battery equalizer with the intelligent fuzzy charge algorithm to charge batteries, and the improved coulometric measurement with accurate residual capacity estimation to estimate the residual capacity of batteries. Because of using the intelligent fuzzy charge algorithm can give different charging current depend on the difference of voltage, capacity and temperature of battery; And because of using the battery equalizer can adjust the voltage of battery. The charger can charge the battery safely without causing any damage. From the experimental results, the charger can achieve the purpose of fast and uniform charge with charging time six (6) to eight (8) hours, the residual capacity estimator can accurate estimate the residual capacity of batteries due to calculating the increment current and considering the aging factor.

This thesis is to design an intelligent battery charger and residual capacity estimator with DSP. This system uses the proposed structure of the series circuit and battery equalizer with the intelligent fuzzy charge algorithm to charge battery, The internal resistance measurement can accurately estimate the residual capacity of battery. Because of using the intelligent fuzzy charge algorithm, it can give different charging current depends on voltage, capacity and temperature of battery. Because of using battery equalizer, it can adjust the voltage of battery to guarantee the battery be charged safely. According to experimental results, the charger can achieve the goal of fast and uniform charge within 6 to 8 hours. On the residual capacity estimator, We measure internal resistance to accurately estimate residual capacity of battery, because internal resistance is affected by environmental temperature, battery corrosion, aging factor and output current .