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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Implementation of a Program Address Generator in a DSP processor / Implementering av en Programadress generator i en DSP processorWaltersson, Roland January 2003 (has links)
<p>The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: </p><p>A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops. </p><p>The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others. </p><p>The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.</p>
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Implementation of a Program Address Generator in a DSP processor / Implementering av en Programadress generator i en DSP processorWaltersson, Roland January 2003 (has links)
The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops. The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others. The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.
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