Reductions in the cost and size of integrated circuits are allowing more and more complex functions to be included in previously simple tools such as lawn-mowers, ovens, and thermostats. Because of this, the process of synthesizing such functions from their initial representation to an optimal VLSI implementation is rarely hand-performed; instead, automated synthesis and optimization tools are a necessity. The factors such tools must take into account are numerous, including area (size), power consumption, and timing factors, to name just a few. Existing tools have traditionally focused upon optimization of two-level representations. However, new technologies such as Field Programmable Gate Arrays (FPGAs) have generated additional interest in three-level representations and structures such as Kronecker Decision Diagrams (KDDs). The reason for this is that when implementing a circuit on an FPGA, the cost of implementing exclusive-or logic is no more than that of traditional AND or OR gates. This dissertation investigates the use of the autocorrelation coefficients in logic synthesis for these types of structures; specifically, whether it is possible to pre-process a function to produce a subset of its autocorrelation coefficients and make use of this information in the choice of a three-level decomposition or of decomposition types within a KDD. This research began as a general investigation into the properties of autocorrelation coefficients of switching functions. Much work has centered around the use of a function's spectral coefficients in logic synthesis; however, very little work has used a function's autocorrelation coefficients. Their use has been investigated in the areas of testing, optimization for Programmable Logic Arrays (PLAs), identification of types of complexity measures, and in various DD-related applications, but in a limited manner. This has likely been due to the complexity in their computation. In order to investigate the uses of these coefficients, a fast computation technique was required, as well as knowledge of their basic properties. Both areas are detailed as part of this work, which demonstrates that it is feasible to quickly compute the autocorrelation coefficients. With these investigations as a foundation we further apply the autocorrelation coefficients to the development of a classification technique. The autocorrelation classes are similar to the spectral classes, but provide significantly different information. The dissertation demonstrates that some of this information highlighted by the autocorrelation classes may allow for the identification of exclusive-or logic within the function or classes of functions. In relation to this, a major contribution of this work involves the design and implementation of algorithms based on these results. The first of these algorithms is used to identify three-level decompositions for functions, and the second to determine decomposition type lists for KDD-representations. Each of these implementations compares well with existing tools, requiring on average less than one second to complete, and performing as well as the existing tools about 70% of the time. / Graduate

Les systèmes de communications sans fil n'ont cessé d'évoluer ces dernières années, poussés par de fortes demandes du marché en systèmes toujours plus autonomes et performants. Ainsi, de nouvelles contraintes de conception sont apparues de manière à mieux prendre en compte les aspects énergétiques et ainsi améliorer la durée de vie des batteries et des circuits. Actuellement, les systèmes de communications numériques sans fil consomment d'importantes quantités d'énergie. D'autre part, la complexité des systèmes croît de génération en génération afin de satisfaire toujours plus d'utilisateurs avec un haut niveau de performances. Dans ce contexte à fortes contraintes, les circuits de type FPGA apparaissent comme une technologie attractive, pouvant supporter des circuits numériques complexes grâce à leur grand nombre de ressources. Pour pouvoir concevoir les futurs systèmes de communications numériques sans fil sur ce type de circuit, les concepteurs de tels systèmes doivent pouvoir estimer la consommation et les performances au plus tôt dans la phase de conception. De cette façon, ils pourront explorer l'espace de conception et effectuer des choix d'implémentation afin d'optimiser leurs systèmes. Durant cette thèse, une méthodologie a été proposée dont les objectifs sont d'estimer rapidement et à haut niveau la consommation de leurs circuits implantés sur FPGA ainsi que leurs performances, d'explorer l'espace de conception, de comparer efficacement plusieurs systèmes entre eux, tout en assurant une bonne précision de l'estimation. La méthodologie repose sur une phase de caractérisation de composants IP matériels ainsi que de leur modélisation en Systeme. Dans un second temps, une représentation haut-niveau du système entier est réalisée à partir de la librairie des modèles Systeme de chaque IP. A travers des simulations haut-niveau, les utilisateurs peuvent tester rapidement de multiples configurations de leur système. Un des caractères innovants de l'approche repose sur l'utilisation de signaux clés qui permettent de tenir compte des comportements dynamiques des composants IP, c-à-d leur temps d'activité (actif/inactif), au sein du système et ainsi obtenir des estimations précises. Les nombreux gains de la méthodologie ont été démontrés à travers plusieurs exemples de systèmes de communications numériques sans fil comme une chaîne de traitement en bande de base de type SISO-OFDM générique, des émetteurs LTE etc. Pour conclure, les limitations ont été adressées et des solutions d'optimisation ont pu être envisagées puis mises en place. / Wireless communication systems are still evolving since the last decades, driven by the growing demand of the electronic market for energy efficient and high performance devices. Thereby, new design constraints have appeared that aim at taking into account power consumption in order to improve battery-life of circuits. Current wireless communication systems commonly dissipate a lot of power. On the other hand, the complexity of such systems keeps on increasing through the generations to always satisfy more users at a high degree of performance. In this highly constrained context, FPGA devices seem to be an attractive technology, able to support complex systems thanks to their important number of resources. According to the FPGA nature, designers need to estimate the power consumption and the performance of their wireless communication systems as soon as possible in the design flow. In this way, they will be able to perform efficient design space exploration and make decisive implementation and optimization choices. Throughout this thesis, a power estimation methodology for hardware-focused FPGA device is described and aims at making design space exploration a lot easier, providing early and fast power and performance estimation at high-level. It also proposes an efficient way to efficiently compare several systems. The methodology is effective through an lP characterisation step and the development of their SystemC models. Then, a high level description of the entire system is realized from the SystemC models that have been previously developed. High-level simulations enable to check the functionality and evaluate the power and performance of the system. One of the contributions consists in monitoring the JP time-activities during the simulation. We show that this has an important impact on both power and performances. The effectiveness of the methodology has been demonstrated throughout several baseband processing chains of the wireless communication domain such as a SISO-OFDM generic chain, LTE transmitters etc. To conclude, the main limitations of the proposed methodology have been investigated and addressed.

FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.

This research investigates three solutions to overcoming portability and scalability concerns in the Evolutionary Hardware (EHW) field. Firstly, the study explores if the V-FPGA—a new, portable Virtual-Reconfigurable-Circuit architecture—is a practical and viable evolution platform. Secondly, the research looks into two possible ways of making EHW systems more scalable: by optimising the system’s genetic algorithm; and by decomposing the solution circuit into smaller, evolvable sub-circuits or modules. GA optimisation is done is by: omitting a canonical GA’s crossover operator (i.e. by using an algorithm); applying evolution constraints; and optimising the fitness function. The circuit decomposition is done in order to demonstrate modular evolution. Three two-bit multiplier circuits and two sub-circuits of a simple, but real-world control circuit are evolved. The results show that the evolved multiplier circuits, when compared to a conventional multiplier, are either equal or more efficient. All the evolved circuits improve two of the four critical paths, and all are unique. Thus, it is experimentally shown that the V-FPGA is a viable hardware-platform on which hardware evolution can be implemented; and how hardware evolution is able to synthesise novel, optimised versions of conventional circuits. By comparing the and canonical GAs, the results verify that optimised GAs can find solutions quicker, and with fewer attempts. Part of the optimisation also includes a comprehensive critical-path analysis, where the findings show that the identification of dependent critical paths is vital in enhancing a GA’s efficiency. Finally, by demonstrating the modular evolution of a finite-state machine’s control circuit, it is found that although the control circuit as a whole makes use of more than double the available hardware resources on the V-FPGA and is therefore not evolvable, the evolution of each state’s sub-circuit is possible. Thus, modular evolution is shown to be a successful tool when dealing with scalability.

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g.\ aerospace). The use of field programmable gate arrays (FPGAs) within safety critical systems is becoming more prevalent due to the design and cost benefits their use provides. The effects of externally caused faults on these safety critical systems cannot be neglected. In particular, high energy particle striking a circuit can cause a voltage change in the circuit known as a soft error. The effects these soft errors will have on the circuit needs to be understood in order to ensure that the systems will function properly in the event soft errors do occur. In this thesis a tool is designed to facilitate the run-time injection of soft errors into a hardware circuit running on a FPGA. The tool allows for the control over the number of injections that can be performed and control over the rate that the injections will occur at. Additionally the tool records time stamps of when injections occur and time stamps of when errors are detected. This recorded data allows for the analysis of designs in conditions prone to soft errors. The implemented tool allows for design time parametrization and run time configuration, allowing a multitude of tests to be run for a single compiled design. The tool also eliminates the need for a host computer after configuration by generating the injection locations and times on the FPGA. Eliminating the host computer allows for faster testing when compared to other methods as data transfer times are greatly reduced. The implemented tool was run on classical examples of redundant structures, such as duplication with comparison and triple modular redundancy as well as a non-redundant structure to establish a baseline. The results of multiple tests run on each structure are analyzed to illustrate the uses of the tool and how the tool may be used to test other designs. / Thesis / Master of Applied Science (MASc)

Time-triggered communication is widely used throughout several industry do- mains, primarily for reliable and real-time capable data transfers. However, existing time-triggered technologies are designed for terrestrial usage and not directly applicable to space applications due to the harsh environment. In- stead, specific hardware must be developed to deal with thermal, mechanical, and especially radiation effects. SpaceWire, as an event-triggered communication technology, has been used for years in a large number of space missions. Its moderate complexity, her- itage, and transmission rates up to 400 MBits/s are one of the main ad- vantages and often without alternatives for on-board computing systems of spacecraft. At present, real-time data transfers are either achieved by prior- itization inside SpaceWire routers or by applying a simplified time-triggered approach. These solutions either imply problems if they are used inside dis- tributed on-board computing systems or in case of networks with more than a single router are required. This work provides a solution for the real-time problem by developing a novel clock synchronization approach. This approach is focused on being compatible with distributed system structures and allows time-triggered data transfers. A significant difference to existing technologies is the remote clock estimation by the use of pulses. They are transferred over the network and remove the need for latency accumulation, which allows the incorporation of standardized SpaceWire equipment. Additionally, local clocks are controlled decentralized and provide different correction capabilities in order to handle oscillator induced uncertainties. All these functionalities are provided by a developed Network Controller (NC), able to isolate the attached network and to control accesses. / Zeitgesteuerte Datenübertragung ist in vielen Industriezweigen weit verbreitet, primär für zuverlässige und echtzeitfähige Kommunikation. Bestehende Technologien sind jedoch für den terrestrischen Gebrauch konzipiert und aufgrund der rauen Umgebung nicht direkt auf Weltraumanwendungen anwendbar. Stattdessen wird spezielle Hardware entwickelt, um Strahlungseffekten zu widerstehen sowie thermischen und mechanischen Belastungen standzuhalten. SpaceWire wurde als ereignisgesteuerte Kommunikationstechnologie entwickelt und wird seit Jahren in einer Vielzahl von Weltraummissionen verwendet. Dessen erfolgreiche Verwendung, überschaubare Komplexität, und Übertragungsraten bis zu 400 MBit/s sind einige seiner Hauptvorteile. Derzeit werden Datenübertragungen in Echtzeit entweder durch Priorisierung innerhalb von SpaceWire Router erreicht, oder durch Anwendung von vereinfachten zeitgesteuerten Ansätzen. Diese Lösungen implizieren entweder Probleme in verteilten Systemarchitekturen oder in SpaceWire Netzwerken mit mehreren Routern. Diese Arbeit beschreibt eine Uhrensynchronisation, die bestimmte Eigenschaften von SpaceWire ausnutzt, um das Echtzeitproblem zu lösen. Der Ansatz ist dabei kompatibel mit verteilten Systemstrukturen und ermöglicht eine zeitgesteuerte Datenübertragung.

In recent years, Light-emitting Diodes (LEDs) have become a promising candidate for backlighting Liquid Crystal Displays [1] (LCDs). Compared with traditional Cold Cathode Fluorescent Lamps (CCFLs) technology, LEDs offer not only better visual quality, but also improved power efficiency. However, to fully utilized LEDs' capability requires dynamic independent control of individual LEDs, which remains as a challenging topic. A FPGA-based hardware system for LED backlight control is proposed in this work. We successfully achieve dynamic adjustment of any individual LED's intensity in each of the three color channels (Red, Green and Blue), in response to a real time incoming video stream. In computing LED intensity, four video content processing algorithms have been implemented and tested, including averaging, histogram equalization, LED zone pattern change detection and non-linear mapping. We also construct two versions of the system. The first employs an embedded processor which performs the above-mentioned algorithms on pre-processed video data; the second embodies the same functionality as the first on fixed hardware logic for better performance and power efficiency. The system servers as the backbone of a consolidated display, which yields better visual quality than common commercial displays, we build in collaboration with a group of researchers from CREOL at UCF.

Turbo codes are a recently discovered class of error correction codes that achieve near-Shannon limit performance. Because of their complexity and highly parallel nature, turbo-coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform. The design's performance and throughput are emphasized in light of its algorithmic improvements, and its flexibility is emphasized as it is ported to a newer, more efficient architecture with more hardware resources. Because this decoder will eventually become the error correction component of a software radio, the design must maintain a high data rate, interface easily with other modules, and conserve hardware resources for future research developments. / Master of Science

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