This thesis presents the CMOS integer-N frequency synthesizer for 2 GHz 802.11 WLAN applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, and a pulse-swallow counter. In pulse-swallow counter, we use less numbers of transistors divide-by-2/3 prescaler to work in high frequency in order to reduce power consumption. We complete the design of pulse-swallow counter for 2-GHz (seven channels) and the 5-GHz (four channels) application. The average power consumption of pulse-swallow counter is 2.49 mW and 2.98 mW for 2-GHz and 5-GHz application respectively. We use Verilog-A language to complete VCO behavior model for frequency synthesizer and utilize the Spectre simulation results justify the feasibility of our proposed frequency synthesizer. The total power consumption of frequency synthesizer is 3.432mW and 4.673mW for 2-GHz and 5-GHz frequency synthesizer, respectively.

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted