The goal of this work is to understand the application of the evolutionary programming approach to the problem of quantum circuit design. This problem is motivated by the following observations: <ul> <li>In order to keep up with the seemingly insatiable demand for computing power our computing devices will continue to shrink, all the way down to the atomic scale, at which point they become quantum mechanical systems. In fact, this event, known as Moore?s Horizon, is likely to occur in less than 25 years. </li> <li> The recent discovery of several quantum algorithms which can solve some interesting problems more efficiently than any known classical algorithm. </li> <li> While we are not yet certain that quantum computers will ever be practical to build, there do now exist the first few astonishing experimental devices capable of briefly manipulating small quantities of quantum information. The programming of these devices is already a nontrivial problem, and as these devices and their algorithms become more complicated this problem will quickly become a significant challenge. </li> </ul> The Evolutionary Programming (EP) approach to problem solving seeks to mimic the processes of evolutionary biology which have resulted in the awesome complexity of living systems, almost all of which are well beyond our current analysis and engineering capabilities. This approach is motivated by the highly successful application of Koza?s Genetic Programming (GP) approach to a variety of circuit design problems, and specifically the preliminary reports byWilliams and Gray and also Rubinstein who applied GP to quantum circuit design. Accompanying this work is software for evolutionary quantum circuit design which incorporates several advances over previous approaches, including: <ul> <li>A formal language for describing parallel quantum circuits out of an arbitary elementary gate set, including gates with one or more parameters. </li> <li> A fitness assessment procedure that measures both average case fidelity with a respect for global phase equivalences, and implementation cost. </li> <li> A Memetic Programming (MP) based reproductive strategy that uses a combination of global genetic and local memetic searches to effectively search through diverse circuit topologies and optimize the parameterized gates they contain. </li> </ul> Several benchmark experiments are performed on small problems which support the conclusion that Evolutionary Programming is a viable approach to quantum circuit design and that further experiments utilizing more computational resources and more problem insight can be expected to yield many new and interesting quantum circuits.

The goal of this work is to understand the application of the evolutionary programming approach to the problem of quantum circuit design. This problem is motivated by the following observations: <ul> <li>In order to keep up with the seemingly insatiable demand for computing power our computing devices will continue to shrink, all the way down to the atomic scale, at which point they become quantum mechanical systems. In fact, this event, known as Moore?s Horizon, is likely to occur in less than 25 years. </li> <li> The recent discovery of several quantum algorithms which can solve some interesting problems more efficiently than any known classical algorithm. </li> <li> While we are not yet certain that quantum computers will ever be practical to build, there do now exist the first few astonishing experimental devices capable of briefly manipulating small quantities of quantum information. The programming of these devices is already a nontrivial problem, and as these devices and their algorithms become more complicated this problem will quickly become a significant challenge. </li> </ul> The Evolutionary Programming (EP) approach to problem solving seeks to mimic the processes of evolutionary biology which have resulted in the awesome complexity of living systems, almost all of which are well beyond our current analysis and engineering capabilities. This approach is motivated by the highly successful application of Koza?s Genetic Programming (GP) approach to a variety of circuit design problems, and specifically the preliminary reports byWilliams and Gray and also Rubinstein who applied GP to quantum circuit design. Accompanying this work is software for evolutionary quantum circuit design which incorporates several advances over previous approaches, including: <ul> <li>A formal language for describing parallel quantum circuits out of an arbitary elementary gate set, including gates with one or more parameters. </li> <li> A fitness assessment procedure that measures both average case fidelity with a respect for global phase equivalences, and implementation cost. </li> <li> A Memetic Programming (MP) based reproductive strategy that uses a combination of global genetic and local memetic searches to effectively search through diverse circuit topologies and optimize the parameterized gates they contain. </li> </ul> Several benchmark experiments are performed on small problems which support the conclusion that Evolutionary Programming is a viable approach to quantum circuit design and that further experiments utilizing more computational resources and more problem insight can be expected to yield many new and interesting quantum circuits.

In this thesis, classical computation is first introduced. Finite quantum systems are considered with D-dimensional Hilbert space, and position x and momentum p taking values in Z(D) (the integers modulo D). An analytic rep resentation of finite quantum systems that use Theta function is presented and considered. The first novel part of this thesis is contribution to study reversible classical CNOT gates and their binary inputs and outputs with reversible cir cuits. Furthermore, a reversible classical Toffoli gates are considered, as well as implementation of a Boolean expression with classical CNOT and Toffoli gates. Reversible circuits with classical CNOT and Toffoli gates are also considered. The second novel part of this thesis the study of quantum computation in terms of CNOT and Toffoli gates. Analytic representations and their zeros are considered, while zeros of the inputs and outputs for quantum CNOT and Toffoli gates are studied. Also, approximate computation of their zeros on the output are calculated. Finally, some quantum circuits are discussed. i

This thesis investigates techniques for the automated optimization of quantum circuits. In the first part we develop an exponential time algorithm for synthesizing minimal depth quantum circuits. We combine this with effective heuristics for reducing the search space, and show how it can be extended to different optimization problems. We then use the algorithm to compute circuits over the Clifford group and T gate for many of the commonly used quantum gates, improving upon the former best known circuits in many cases. In the second part, we present a polynomial time algorithm for the re-synthesis of CNOT and T gate circuits while reducing the number of phase gates and parallelizing them. We then describe different methods for expanding this algorithm to optimize circuits over Clifford and T gates.

This thesis studies quantum coherence in macroscopic and mesoscopic dissipative electrical circuits, including LC circuits, microwave resonators, and Josephson junctions. For the LC resonator and the terminated transmission line microwave resonator, second quantization is carried out for the lossless system and dissipation in modeled as the coupling to a bath of harmonic oscillators. Stationary states of the linear and nonlinear resonator circuits as well as the associated energy levels are found, and the time evolution of uncertainty relations for the observables such as flux, charge, current, and voltage are obtained. Coherent states of both the lossless and weakly dissipative circuits are studied within a quantum optical approach based on a Fokker-Plank equation for the P-representation of the density matrix which has been utilized to obtain time-variations of the averages and uncertainties of circuit observables. Macroscopic quantum tunneling is addressed for a driven dissipative Josephson resonator from its metastable current state to the continuum of stable voltage states. The Caldeira-Leggett method and the instanton path integral technique have been used to find the tunneling rate of a driven Josephson junction from a zero-voltage state to the continuum of the voltage states in the presence of dissipation. Upper and lower bounds are obtained for the tunneling rate at the intermediate loss and approximate closed form expressions are derived for the overdamped and underdamped limits.

This thesis studies quantum coherence in macroscopic and mesoscopic dissipative electrical circuits, including LC circuits, microwave resonators, and Josephson junctions. For the LC resonator and the terminated transmission line microwave resonator, second quantization is carried out for the lossless system and dissipation in modeled as the coupling to a bath of harmonic oscillators. Stationary states of the linear and nonlinear resonator circuits as well as the associated energy levels are found, and the time evolution of uncertainty relations for the observables such as flux, charge, current, and voltage are obtained. Coherent states of both the lossless and weakly dissipative circuits are studied within a quantum optical approach based on a Fokker-Plank equation for the P-representation of the density matrix which has been utilized to obtain time-variations of the averages and uncertainties of circuit observables. Macroscopic quantum tunneling is addressed for a driven dissipative Josephson resonator from its metastable current state to the continuum of stable voltage states. The Caldeira-Leggett method and the instanton path integral technique have been used to find the tunneling rate of a driven Josephson junction from a zero-voltage state to the continuum of the voltage states in the presence of dissipation. Upper and lower bounds are obtained for the tunneling rate at the intermediate loss and approximate closed form expressions are derived for the overdamped and underdamped limits.

This thesis investigates techniques for the automated optimization of quantum circuits. In the first part we develop an exponential time algorithm for synthesizing minimal depth quantum circuits. We combine this with effective heuristics for reducing the search space, and show how it can be extended to different optimization problems. We then use the algorithm to compute circuits over the Clifford group and T gate for many of the commonly used quantum gates, improving upon the former best known circuits in many cases. In the second part, we present a polynomial time algorithm for the re-synthesis of CNOT and T gate circuits while reducing the number of phase gates and parallelizing them. We then describe different methods for expanding this algorithm to optimize circuits over Clifford and T gates.

Quantum information processing is of interest as it offers the potential for a new generation of very powerful computers supporting novel computational paradigms. Over the last couple of decades, different aspects of quantum computers ranging from quantum algorithms to quantum physical design have received growing attention. One of the most important research areas is the synthesis and post-synthesis optimization of reversible and quantum circuits. Many synthesis and optimization approaches can be found in the literature, yet, due to the complexity of the problem, finding approaches leading to optimal, or near optimal, results is still an open problem. The synthesized circuits are usually evaluated based on quantum cost models. Therefore, they are often technology mapped to circuits of more primitive gates. To this end, various technology mapping approaches have also been proposed in the past few years. Related work shows an existing gap in optimized technology mapping for reversible and quantum circuits. In this dissertation, an optimized technology mapping design flow is introduced for mapping reversible circuits to quantum circuits. The contributions of this dissertation are classified as follows: - New reversible circuit optimization methods. - Optimized reversible to quantum mapping approaches. - New quantum gate libraries and new cost models for reversible gates based on the new libraries. - Quantum circuit optimization approaches. The steps above, form an optimized flow for mapping reversible circuits to quantum circuits. At each step of the design flow optimized and consistent approaches are suggested with the goal of reducing the quantum cost of the synthesized reversible circuits. The evaluations show that the proposed mapping methodology leads to significant improvement in the quantum cost of the existing benchmark circuits. / Graduate

Quantum computing is rapidly growing as well as the interest in it, not only by the scientific community but also by impacting realities such as IBM and Microsoft, which are aiming to be the first to acquire quantum supremacy, a meaningful theoretical step in quantum research where a quantum computer would win undisputed once and for all the race with traditional supercomputers. One of the main enabling technologies for quantum computing is photonics, that features photons as the quantum actors "interacting" in a PIC, mostly based on the mature silicon technology of electronics. This thesis presents my work on electronic control architecture for PICs. The work is based on PICs fabricated in Fondazione Bruno Kessler (FBK) with silicon and dielectric technology, using silicon oxynitride (SiON) as the wave-guiding dielectric medium. The PIC were integrated on Printed Circuit Boards through wire-bonding technique, realizing modules easily integrated and re-configured with the custom made interposer board and the multiple voltage drivers that are at the core of the electronic architecture. Then, both the thermistors and the photodiodes were characterized. A custom firmware was then developed to control the thermistors by providing an analog voltage in the 0-12 V range, and each of those elements effectively acts as a Degree of Freedom (DoF) for the photonic architecture. In addition, to validate the results obtained by voltage driving the phase-shifters, the theoretical output of a single Mach Zehnder Interferometer (MZI) was computed and compared to the one achieved experimentally. Furthermore, such systems are controlled in a closed loop by using as a feedback the photocurrent produced by photodiodes placed either on each output of the PIC or homogeneously integrated withing the PIC itself. Finally, a secondary source of feedback was developed and investigated. Although it is a feasible method to estimate the light intensities of outputs, basing the feedback on invasive sensors implies strict bindings during the design stage and limits the measurable scenarios of a PIC, thus in this thesis I also propose an optical tool to arbitrary tune and control a PIC based solely on camera inspection. By using such technique it would be possible not only to achieve comparable results with respect to the traditional invasive sensing, but also to inspect the system configuration in any section of the chip, without being limited to only the regions where photodiodes would be present.

Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: Thorough layout verification of superconductor integrated circuits goes beyond design rule checking and parameter value extraction. The former is used to verify adherence to process design rules, and the latter to determine the element values of components such as inductors and resistors and Josephson junction critical currents. Still, neither gives much warning against subtle layout errors that could result in unintended parasitic elements, or a circuit that does not reflect the original circuit topology. A specialized implementation for Cadence Virtuoso allows layout-versus-schematic verification, but it is limited both to commercial software and in terms of its usefulness. Parameter extraction software such as InductEx is used to extract the component element values of a circuit from its layout if the circuit topology is provided as a netlist, which is mostly created by the designer. However, the element values are extracted for the supplied topology, even if a layout mistake such as creating a connection to the wrong node or a mistake in the netlist results in a model mismatch. After a failed verification, further diagnosis is required to determine whether the error is indeed in the layout or in the input topology - prolonging the verification process significantly. Here we present a free-standing layout-versus-schematic verification toolkit for superconductive integrated circuits, and discuss its implementation after systematically considering the algorithms at its core. We demonstrate results of the layout-versus-schematic verification and how the layout-versus-schematic toolkit is used as a whole in conjunction with InductEx to perform automated parameter extraction for cell-level layout verification. The current version of this toolkit provides the user with three stand-alone tools that are best used in conjunction with InductEx: A GDSII file flattener, a layout-to-schematic netlist extractor (with the option of viewing a pictorial reconstruction of the netlist and schematic) and a netlist comparison tool by which the user can determine whether a layout agrees with an input schematic. We conclude that the netlist comparison and viewing tool provides a valuable method for expediting the layout verification process, making it more efficient and minimizing the chances of mistakes. In its current form the layout-to schematic tool is still limited in that it cannot yet fully support circuits with mutual coupling. Although many improvements can still be made to this toolkit, the implemented version of these tools can already provide great benefit to Rapid Single Flux quantum (RSFQ) cell designers. / AFRIKAANSE OPSOMMING: Deeglike uitleg verifikasie van supergeleier geïntegreerde stroombane strek verder as bloot die nasien van ontwerpreëls en die onttrekking van parameter waardes. Eersgenoemde word gebruik om vas te stel of daar voldoen word aan die proses se ontwerpreëls, en laasgenoemde om die waardes van komponente soos induktors en resistors en die kritiese strome van Josephson aansluitings te bepaal. Nogtans bied nie een van hulle veel waarskuwing teen subtiele uitlegfoute wat onbeplande parasitiese elemente kan veroorsaak nie, of teen ‘n stroombaan wat nie die oorspronklike stroombaan topologie weerspieël nie. ‘n Gespesialiseerde implementasie van Cadence Virtuoso maak LVS (layout-versus-schematic) verifikasie moontlik, maar dit is beperk tot kommersiële sagteware en ook beperk in terme van bruikbaarheid. Parameter onttrekking sagteware soos InductEx word gebruik om waardes van die komponent-elemente van ‘n stroombaan vanuit die uitleg te onttrek wanneeer die stroombaan topologie as ‘n netlist, wat meestal deur die ontwerper geskep is, voorsien word. Die elementwaardes word egter onttrek volgens die topologie wat verskaf is, al is daar uitlegfoute, soos byvoorbeeld wanneer ‘n koppeling met ‘n verkeerde node plaasvind, of wanneer daar netlist foute is wat modelteenstrydighede veroorsaak. Na ‘n mislukte verifikasie poging word verdere diagnostiese stappe gedoen om te bepaal of die fout in die uitleg lê, of in die spesifieke topologie wat verskaf is, wat natuurlik die verifikasieproses aansienlik verleng. Hier stel ons ‘n vrystaande LVS verifikasie sagteware-pakket vir supergeleier geïntegreerde stroombane bekend, en bespreek, deur middel van die algoritmes wat die kern daarvan uitmaak, die implementering van hierdie sagteware-toestel. Ons bied die resultate van die LVS verifikasie aan en wys hoe die LVS sagteware toestel as geheel saam met InductEx gebruik kan word om automatiese parameter uittrekking vir sel-vlak uitleg verifikasie te berwerkstellig. Die huidige weergawe van die pakket bied die verbruiker drie alleenstaande programme wat verkieslik saam met InductEx gebruik moet word: ‘n GDSII “file flattener”, ‘n uitleg-tot-schematiese diagram netlist ekstraktor (met die opsie om ‘n herkonstruktueerde beeld van netlist en skematiese diagram te besigtig) en ‘n netlist vergelyking toestel waarmee die verbruiker kan vasstel of ‘n uitleg met ‘n oorspronklike skematiese diagram ooreenstem. Ons lei af dat die netlist vergelyking toestel ‘n waardevolle metode bied om die uitleg verifikasie proses te bespoedig en vergemaklik en die kanse van foute te minimaliseer. In sy huidige vorm is die uitleg-tot-skematiese diagram toestel beperk omdat dit nog nie stroombane met koppeling kan steun nie.