Digital signal processors and their variants have provided significant benefit to efficient implementation of Physical Layer (PHY) of Open Systems Interconnection (OSI) model’s seven-layer protocol processing stack compared to the general purpose processors. Protocol processors promise to provide a similar advantage for implementing higher layers in the (OSI)'s seven-layer model. This thesis addresses the problem of designing customizable coarse-grain reconfigurable protocol processing fabrics as a solution to achieving high performance and computational efficiency. A key requirement that this thesis addresses is the ability to not only adapt to varying applications and standards, and different modes in each standard but also to time varying load and performance demands while maintaining quality of service.This thesis presents a tile-based multicore protocol processing architecture that can be customized at design time to meet the requirements of the target application. The architecture can then be reconfigured at boot time and tuned to suit the desired use-case. This architecture includes a packet-oriented memory system that has deterministic access time and access energy costs, and hence can be accurately dimensioned to fulfill the requirements of the desired use-case. Moreover, to maintain quality of service as predicted, while minimizing the use of energy and resources, this architecture encompasses an elastic management scheme that controls run-time configuration to deploy processing resources based on use-case and traffic demands.To evaluate the architecture presented in this thesis, different case studies were conducted while quantitative and qualitative metrics were used for assessment. Energy-delay product, energy efficiency, area efficiency and throughput show the improvements that were achieved using the processing cores and the memory of the presented architecture, compared with other solutions. Furthermore, the results show the reduction in latency and power consumption required to evaluate controlling states when using the elastic management scheme. The elasticity of the scheme also resulted in reducing the total area required for the controllers that serve multiple processing cores in comparison with other designs. Finally, the results validate the ability of the presented architecture to support quality of service without misutilizing available energy during a real-life case study of a multi-participant Voice Over Internet Protocol (VOIP) call. / <p>QC 20161028</p>

This thesis work builds on the concept of reconfiguring the antenna properties (frequency, polarization, radiation pattern) using Radio Frequency (RF) Micro Electro Mechanical Systems (MEMS). This is a part of the overall research performed at the RF Micro/Nano Electro Mechanical Systems (uNeMS) Laboratory at Utah State University, which includes design, microfabrication, test, and characterization of uNeMS integrated cognitive wireless communication systems (Appendix A). In the first step, a compact and broadband Planar Inverted F Antenna (PIFA) is designed with a goal to accommodate reconfigurability at a later stage. Then, a Frequency Reconfigurable Antenna (FRA) is designed using MEMS switches to switch between the Public Safety (PS) bands, 152-162 MHz and 406-512 MHz, while maintaining the integrity of radiation pattern for each band. Finally, robust mechanical designs of the RF MEMS switches accompanied by different analyses have been performed. These analyses are instrumental in obtaining high yield, reliable, robust microfabrication processes including thin film metal deposition and patterning.

Reconfigurable computing is a method of development that provides a developer with the ability to reprogram a hardware device. In the specific case of FPGAs this allows for rapid and cost effective implementation of hardware devices when compared to standard a ASIC design, coupled with an increase in performance when compared to software based solutions. With the advent of development tools such as Celoxica's DK package and Xilinx's Forge package, that support languages traditionally associated with software development, a change in the skill sets required to develop FPGA solutions from hardware designers to software programmers is possible and perhaps desirable to increase the adoption of FPGA technologies. To support developers with these skill sets tools should closely mirror current software development tools in terms of language, syntax and methodology, while at the same time both transparently and automatically take advantage of as much of the increased performance that reconfigurable architectures can provide over traditional software architectures by utilizing the parallelism and the ability to create arbitrary depth pipelines which is not present in traditional microprocessor designs. A common feature of many programming languages that is not supported by many higher level design tools is recursion. Recursion is a powerful method used to elegantly describe many algorithms. Recursion is typically implemented by using a stack to store arguments, context and a return address for function calls. This however limits the controlling hardware to running only a single function at any moment which eliminates an algorithm's ability to take advantage of the parallelism available between successive iterations of a recursive function. This squanders the high amount of parallelism provided by the resources on the FPGA thus reducing the performance of the recursive algorithm. This thesis presents a method to address the lack of support for recursion in design tools that exploits the parallelism available between recursive calls. It does this by unrolling the recursion into a pipeline, in a similar manner to the pipeline obtained from loop unrolling, and then streaming the data through the resulting pipeline. However essential differences between loops and recursive functions such as multiple recursive calls in a function, and hence multiple unrollings, and post-recursive statements add further complexity to the issue of unrolling as the pipeline may take a non-linear shape and contain heterogeneous stages. Unrolling the recursive function on the FPGA increases the parallelism available, however the depth of the pipline and therefore the amount of parallelism available, is limited by the finite resources on the FPGA. To make efficient use of the resources on the FPGA the system must be able to unroll the function in a way to best suit the input but also must ensure that the function is not unrolled past its maximum recursive depth. A trivial solution such as unrolling on-demand introduces a latency into the system when a further instance of the function is unrolled that reduces overall performance. To reduce this penalty it is desirable for the system to be able to predict the behaviour of the recursive function based on the input data and unroll the function to a suitable length prior to it being required. Accurate prediction is possible in cases where the condition for recursion is a simple function on the arguments, however in cases where the condition for recursion is based on complex functions, such as the entire recursive function, accurate prediction is not possible. In situations such as this a heuristic is used which provides a close approximation to the correct depth of recursion at any given time. This prediction allows the system to reduce the performance penalty from real time unrolling without over utilization of the the FPGA resources. Results obtained demonstrate the increase in performance for various recursive functions obtained from the increased parallelism, when compared to a stack based implementation on the same device. In certain instances due to constraints on hardware availability results were gained from device simulation using a simulator developed for this purpose. Details of this simulator are presented in this thesis.

With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However, multiplier is always a fundamental component and influences the power consumption and performance much in many DSP and multimedia applications. Therefore, multiplier is the crucial design and need to be concerned at first. In these systems, the data width of input data is various because the different applications are operated in the same system. According to this characteristic of input data, this paper presents architecture of reconfigurable multiplier without the necessity to completely reconfigure the internal layout of a programmable device. The multiplier employs the Booth algorithm which reduces the partial products to half to implement the sign multiplication. In order to reduce power consumption, the proposed multiplier introduces the clock gating technique to disable the circuit which does not need to be computed. Moreover, the energy-efficient multiplier presented in this thesis can perform multiplication with different data widths to further decrease power dissipation and enhance performance. In this work, we proposed two versions of multipliers. The first version is reconfigurable pipelined Booth multiplier, which can perform one n by n multiplication or two n/2 by n/2 multiplications concurrently. When the multiplier performs n-bit multiplication, it can reduce power consumption by disabling the unnecessary blocks according to the input data. The second version further deploys the truncated functionality to provide different way to make multiplication more energy-efficient. Experiment shows that the proposed multipliers can perform multiplication with less energy and lower power dissipation. It is certain that the more functions the design provides, the more area it will cost.

This research is focused on identifying an appropriate design for a reconfigurable Body Area Network (BAN). In order to investigate the benefits and drawbacks of the proposed design, a BAN system prototype was built. This system consists of two distinct node types: a slave node and a master node. These nodes communicate using ZigBee radio transceivers. The microcontroller-based slave node acquires sensor data and transmits digitized samples to the master node. The master node is FPGA-based and runs uClinux on a soft-core microcontroller. The purpose of the master node is to receive, process and store digitized sensor data. In order to verify the operation of the BAN system prototype and demonstrate reconfigurability, a specific application was required. Pattern recognition in electrocardiogram (ECG) data was the application used in this work and the MIT-BIH Arrhythmia Database was used as the known data source for verification. A custom test platform was designed and built for the purpose of injecting data from the MIT-BIH Arrhythmia Database into the BAN system. The BAN system designed and built in this work demonstrates the ability to record raw ECG data, detect R-peaks, calculate and record R-R intervals, detect premature ventricular and atrial contractions. As this thesis will identify, many aspects of this BAN system were designed to be highly reconfigurable allowing it to be used for a wide range of BAN applications, in addition to pattern recognition of ECG data.

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.

The object detection framework developed by Viola and Jones has become very popular due to its high quality and detection speed. However, the complexity of the computation required to train a detector makes it difficult to develop and test potential improvements to this algorithm or train detectors in the field. In this thesis, a configurable, high-performance FPGA architecture is presented to accelerate this training process. The architecture, structured as a systolic array of pipelined compute engines, is constructed to provide high throughput and make efficient use of the available external memory bandwidth. Extensions to the Viola-Jones detection framework are implemented to demonstrate the flexibility of the architecture. The design is implemented on a Xilinx ML605 development platform running at 200~MHz and obtains a 15-fold speed-up over a multi-threaded OpenCV implementation running on a high-end processor.

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.

The object detection framework developed by Viola and Jones has become very popular due to its high quality and detection speed. However, the complexity of the computation required to train a detector makes it difficult to develop and test potential improvements to this algorithm or train detectors in the field. In this thesis, a configurable, high-performance FPGA architecture is presented to accelerate this training process. The architecture, structured as a systolic array of pipelined compute engines, is constructed to provide high throughput and make efficient use of the available external memory bandwidth. Extensions to the Viola-Jones detection framework are implemented to demonstrate the flexibility of the architecture. The design is implemented on a Xilinx ML605 development platform running at 200~MHz and obtains a 15-fold speed-up over a multi-threaded OpenCV implementation running on a high-end processor.

Le besoin de concevoir des systèmes de détection efficaces de diverses substances afin d'améliorer le contrôle de qualité et la sécurité environnementale, nous amène à chercher de nouvelles approches pour contourner les problèmes reliés aux systèmes de détection actuels, tels leur taille, coût, sélectivité et consommation d'énergie. Il est aussi souhaitable de définir un modèle de développement qui ne soit pas contraint par le besoin d'une connaissance précise des processus physiques sous-jacents, souvent inconnus. Ce mémoire décrit la mise en oeuvre partielle d'un dispositif permettant d'identifier et de mesurer la concentration de substances fluorophoriques dans un milieu optique typique (Solution liquide ou suspension dans un fluide). La méthode est basée sur des mesures de fluorescence multispectrales, réalisées en excitant une substance inconnue avec une ou plusieurs diodes électroluminescentes qui couvrent un intervalle de longueurs d'ondes donné. La conception du détecteur photoélectrique repose sur la propriété inhérente des diodes électroluminescentes d'agir comme détecteurs photoélectriques quand elles sont polarisées à l'envers, et cela en offrant une réponse spectrale qui dépend de leur couleur. Dans ce mémoire, on propose un système dont l'entrée est composée d'une diode excitatrice et d'un ensemble de diodes électroluminescentes de différentes couleurs qui détectent la lumière à différentes longueurs d'ondes. Les données acquises par les photodiodes sont transmises à un système d'amplification puis à un convertisseur analogique numérique avant d'être acheminées vers un microcontrôleur implémenté sur une puce FPGA. Ce dernier permet de commander le processus de saisie des données et l'affichage des résultats obtenus quant au type et à la concentration des données obtenues. Un réseau de neurones artificiel (RNA) codé en logiciel réalise le traitement des données requis. Ce mémoire couvre tous les aspects du design sauf celui du RNA. ______________________________________________________________________________ MOTS-CLÉS DE L’AUTEUR : Mesure de fluorescence, Photodiode, FPGA, MicroBlaze.