A compact, frequency-reconfigurable filtenna with sharp out-of-band rejection in both its wideband and continuously tunable narrowband states is presented. It is intended for use in cognitive radio applications. The wideband state is the sensing state and operationally covers 2.35-4.98 GHz. The narrowband states are intended to cover communications within the 3.05-4.39 GHz range, which completely covers the Worldwide Interoperability for Microwave Access (WiMAX) band and the satellite communications C-band. A p-i-n diode is employed to switch between these wide and narrowband operational states. Two varactor diodes are used to shift the operational frequencies continuously among the narrowband states. The filtenna consists of a funnel-shaped monopole augmented with a reconfigurable filter; it has a compact electrical size: 0.235 lambda(L) x 0.392 lambda(L), where the wavelength lambda(L) corresponds to the lower bound of its operational frequencies. The measured reflection coefficients, radiation patterns, and realized gains for both operational states are in good agreement with their simulated values.

Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabric is limited by the size of instruction buffers associated with each Compute element. When an application cannot be accommodated entirely, application is partitioned such that each of these partitions can be executed on the reconfigurable fabric. These partitions are scheduled by an orchestrator. The orchestrator employs dynamic dataflow execution paradigm. Dynamic dataflow execution paradigm has inherent support for synchronization and helps in exploitation of parallelism that exists across application partitions. In this thesis, we present a compiler that targets such CGRAs. The compiler presented in this thesis is capable of accepting applications specified in C89 standard. To enable architectural design space exploration, the compiler is designed such that it can be customized for several instances of CGRAs employing dataflow execution paradigm at the orchestrator. This can be achieved by specifying the appropriate configuration parameters to the compiler. The focus of this thesis is to provide efficient support for various kinds of parallelism while ensuring correctness. The compiler is designed to support fine-grained task level parallelism that exists across iterations of loops and function calls. Additionally, compiler can also support pipeline parallelism, where a loop is split into multiple stages that execute in a pipelined manner. The prototype compiler, which targets multiple instances of a CGRA, is demonstrated in this thesis. We used this compiler to target multiple variants of CGRAs employing dataflow execution paradigm. We varied the reconfigur-able fabric, orchestration mechanism employed, size of instruction buffers. We also choose applications from two different domains viz. cryptography and linear algebra. The execution time of the CGRA (the best among all instances) is compared against an Intel Quad core processor. Cryptography applications show a performance improvement ranging from more than one order of magnitude to close to two orders of magnitude. These applications have large amounts of ILP and our compiler could successfully expose the ILP available in these applications. Further, the domain customization also played an important role in achieving good performance. We employed two custom functional units for accelerating Cryptography applications and compiler could efficiently use them. In linear algebra kernels we observe multiple iterations of the loop executing in parallel, effectively exploiting loop-level parallelism at runtime. Inspite of this we notice close to an order of magnitude performance degradation. The reason for this degradation can be attributed to the use of non-pipelined floating point units, and the delays involved in accessing memory. Pipeline parallelism was demonstrated using this compiler for FFT and QR factorization. Thus, the compiler is capable of efficiently supporting different kinds of parallelism and can support complete C89 standard. Further, the compiler can also support different instances of CGRAs employing dataflow execution paradigm.

Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / The advent of adaptive computers built from re-programmable logic devices presents a potential solution for meeting the data processing requirements of the new era of Earth monitoring satellites to be launched by the National Aeronautics and Space Administration (NASA) Earth Science Enterprise project. The Earth Observing System (EOS) AM-1 spacecraft, the first satellite of this new era, will produce in only six months as much data as NASA has collected to this date. As a consequence, the Earth Science Data and Information System (ESDIS) project is building high performance and highly costly parallel processing systems to address the real-time data production requirements. Together with the high performance front-end ingest and level 0 processing microcircuits developed in-house at the Goddard Space Flight Center’s (GSFC) Data Systems Technology Division (DSTD), adaptive computers present a possible alternative to traditional CPU-based systems to increase the performance while reducing the cost of satellite telemetry processing systems. The Adaptive Scientific Data Processing (ASDP) project has been investigating the use of adaptive computers in the implementation of space borne scientific data processing systems. An order of magnitude processing speed acceleration over high-end workstations has been demonstrated for both level 1 and level 3 algorithms. This paper discusses the use of adaptive computing in satellite telemetry processing systems, level 1 and beyond. Primarily, it describes the efforts and presents the results of two prototypes developed by the ASDP project. The limitations of the current state of the technology are discussed and the expected improvements to facilitate the adoption of adaptive computers are presented. Finally, future work of the ASDP project is discussed.

A mixed-signal reconfigurable platform gives the designer the choice of implementing systems using the benefits of both analog and digital circuits. The subject of this research is the implementation and application of mixed-signal reconfigurable systems utilizing floating-gate transistors and field programmable analog/digital arrays. Basic analog circuits using floating-gate CMOS devices have been developed for this research. Floating-gate based analog circuits reduce the effects of inherent property mismatch present in analog circuits. Various circuit blocks including current mirrors, gilbert multipliers, and $G_m-C$ filters were designed and experimentally demonstrated to show reduced mismatch effects. Such floating-gate transistors and circuits are the basis for the reconfigurable systems developed in this research. To enable high-performance reconfigurable systems, sub-micron and sub-$100 nm$ CMOS process nodes were used in this research. Scaling of Floating-gate devices is a key issue at small nodes. Test structures were created to verify the programming capability for floating-gate devices at various process nodes. Experimental results show scalability of floating-gate devices along with effective charge programming ability. A floating-gate based reconfigurable mixed-signal platform using Field-Programmable Array of Analog-Digital Devices (FPAADD) has been created and experimentally verified. Further FPAADD systems augmented with a CPU based digital back-end were developed to enable greater applications for such reconfigurable systems. Experimental functionality and circuits/systems created using FPAADD based systems were demonstrated for this research work.

Adaptive array antennas use has been limited to non-commercial applications due to their high cost and hardware complexity. The implementation cost of adaptive array antennas can be kept to a minimum by using cost effective antennas, reducing the number of elements in the array and implementing efficient beamforming techniques. This thesis presents techniques for the design of adaptive array antennas which will enable their cost effective implementation in wireless communication systems. The techniques are investigated from three perspectives, namely, reconfigurable antenna design, wide scan array design and single-port beamforming technique. A novel single-feed polarisation reconfigurable antenna design is proposed in the first stage of this study. Different polarisation states, namely, linear polarisation (LP), left-hand circular polarisation (LHCP) and right-hand circular polarisation (RHCP), are achieved by perturbing the shape of the main radiating structure of the antenna. The proposed antenna exhibits good axial ratio (< 3 dB at 2.4 GHz) and has high radiation efficiency in both polarisation modes (91.5 % - LHCP and 86.9 % - RHCP). With a compact single feeding structure, the antenna is suitable for implementation in wireless communication devices. The second stage of the study presents the design procedure of wide scan adaptive array antennas with reduced number of elements. Adaptive array antennas with limited number of elements have limited scanning range, reduced angular scanning resolution and high sidelobe levels. To date, design synthesis of adaptive array antennas has been targeted on arrays with a large number of elements. This thesis presents a comprehensive analysis of adaptive array antennas with less than 10 elements. Different array configurations are analysed and various array design parameters such as number of elements, separation between elements and orientation of the elements are analysed in terms of their 3 dB scan range. The proposed array, the 3-faceted array, achieves a scanning range up to ±70°, which is higher than ±56° obtained from the Uniform Linear Array. The faceted arrays are then evaluated in the context of adaptive beamforming properties. It was shown that the 3-faceted array is suitable for adaptive array applications in wireless communication systems as it achieves the highest directivity compared to other faceted structures. The 3-faceted array is then synthesised for low sidelobe level. Phase correction together with amplitude tapering technique is applied to the 3-faceted array. The use of conventional and tuneable windowing techniques on the 3- faceted array is also analysed. The final stage of the study investigates beamforming techniques for the adaptive array antenna. In the first part, beamforming algorithms using different performance criteria, which include maximum signal-to noise-ratio (SINR), minimum (mean-square Error) MSE and power minimisation, are evaluated. In the second part, single-port beamforming techniques are explored. In previous single-port beamforming methods, the spatial information of the signals is not fully recovered and this limits the use of conventional adaptive beamforming algorithms. In this thesis, a novel signal estimation technique using pseudo-inverse function for single-port beamforming is proposed. The proposed polarisation reconfigurable antenna, the 3-faceted array antenna and the single-port beamforming technique achieve the required performance, which suggests the potential of adaptive array antennas to be deployed commercially, especially in wireless communication industry.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / Legacy telemetry systems, although widely deployed, are being severely taxed to support the high data rate requirements of advanced aircraft and missile platforms. Increasing data rates, in conjunction with loss of spectrum have created a need to use available spectrum more efficiently. In response to this, new modulation techniques have been developed which offer more data capacity in the same operating bandwidth. Demodulation of these new waveforms is a computationally challenging task, especially at high data rates. This paper describes the design, implementation and performance of a high-speed, multi-mode demodulator for the Advanced Range Telemetry (ARTM) program which meets these challenges.

International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Traditional communication hardware has focused on modular architectures. Now, with the incoming high speed DSP and FPGAs a shift from traditional modular architecture to reconfigurable architecture has taken place. The nature of this architecture allows to optimize various telemetry applications in a single platform. This paper describes a reconfigurable multi channel communication system.

No description available.

Mobile devices have become a dominant tool in our daily lives. Business and personal usage has escalated tremendously since the emergence of smartphones and tablets. The combination of powerful processing in mobile devices, such as smartphones and the Internet, have established a new era for communications systems. This has put further pressure on the performance and efficiency of telecommunications systems in delivering the aspirations of users. Mobile device users no longer want devices that merely perform phone calls and messaging. Rather, they look for further interactive applications such as video streaming, navigation and real time social interaction. Such applications require a new set of hardware and standards. The WiFi (IEEE 802.11) standard has been at the forefront of reliable and high-speed internet access telecommunications. This is due to its high signal quality (quality of service) and speed (throughput). However, its limited availability and short range highlights the need for further protocols, in particular when far away from access points or base stations. This led to the emergence of 3G followed by 4G and the upcoming 5G standard that, if fully realised, will provide another dimension in “anywhere, anytime internet connectivity.” On the other hand, the WiMAX (IEEE 802.16) standard promises to exceed the WiFi signal coverage range. The coverage range could be extended to kilometres at least with a better or similar WiFi signal level. This thesis considers a dynamically reconfigurable architecture that is capable of processing various modules within telecommunications systems. Forward error correction, coder and navigation modules are deployed in a unified low power communication platform. These modules have been selected since they are among those with the highest demand in terms of processing power, strict processing time or throughput. The modules are mainly realised within WiFi and WiMAX systems in addition to global positioning systems (GPS). The idea behind the selection of these modules is to investigate the possibility of designing an architecture capable of processing various systems and dynamically reconfiguring between them. The GPS system is a power-hungry application and, at the same time, it is not needed all of the time. Hence, one key idea presented in this thesis is to effectively exploit the dynamic reconfiguration capability so as to reconfigure the architecture (GPS) when it is not needed in order to process another needed application or function such as WiFi or WiMAX. This will allow lower energy consumption and the optimum usage of the hardware available on the device. This work investigates the major current coarse-grain reconfigurable architectures. A novel multi-rate convolution encoder is then designed and realised as a reconfigurable fabric. This demonstrates the ability to adapt the algorithms involved to meet various requirements. A throughput of between 200 and 800 Mbps has been achieved for the rates 1/2 to 7/8, which is a great achievement for the proposed novel architecture. A reconfigurable interleaver is designed as a standalone fabric and on a dynamically reconfigurable processor. High throughputs exceeding 90 Mbps are achieved for the various supported block sizes. The Reed Solomon coder is the next challenging system to be designed into a dynamically reconfigurable processor. A novel Galois Field multiplier is designed and integrated into the developed Reed Solomon reconfigurable processor. As a result of this work, throughputs of 200Mbps and 93Mbps respectively for RS encoding and decoding are achieved. A GPS correlation module is also investigated in this work. This is the main part of the GPS receiver responsible for continuously tracking GPS satellites and extracting messages from them. The challenging aspect of this part is its real-time nature and the associated critical time constraints. This work resulted in a novel dynamically reconfigurable multi-channel GPS correlator with up to 72 simultaneous channels. This work is a contribution towards a global unified processing platform that is capable of processing communication-related operations efficiently and dynamically with minimum energy consumption.