It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a microprocessor with one or many reconfigurable computing units. Thus, it might cause multiple devices to compete for System Bus that caused bus collision. And then the system performance will be limited on the bandwidth. Based on these shortcomings, this paper proposes an architecture which combines DDRx memory with a reconfigurable FPGA to construct a module with both storage and computing functions called Brain module. Brain module¡¦s instruction set is created through the extension of DDRx memory instruction. We also design the brain module controller and Hardware Management Unit. According to the definition of Software-Hardware Co-communication, the dynamically constructed Hardware Management Unit will create a hardware function call mechanism. We also establish internal data switching mechanism to achieve transmission data between memory and reconfigurable computing internal the controller. Thus, it can reduce the workload of System Bus and integrate hardware and software work. In software structure, we inherit the traditional programming language and integrate program data area and reconfigurable computing data area. Brain module data is accessed through memory mapping I/O. User can implement the software-hardware co-work by integrated programming environment,

Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly expanding to meet the requirements of compute intense real and non-real time applications in key areas such as cryptography, signal/radar processing and other areas. To meet the demands of such applications, a parallel single-chip heterogeneous Hybrid Data/Command Architecture (HDCA) has been proposed. This single-chip multiprocessor architecture system is reconfigurable at three levels: application, node and processor level. It is currently being developed and experimentally verified via a three phase prototyping process. A first phase prototype with very limited functionality has been developed. This initial prototype was used as a base to make further enhancements to improve functionality and performance resulting in a second phase virtual prototype, which is the subject of this thesis. In the work reported here, major contributions are in further enhancing the functionality of the system by adding additional processors, by making the system reconfigurable at the node level, by enhancing the ability of the system to fork to more than two processes and by designing some more complex real/non-real time applications which make use of and can be used to test and evaluate enhanced and new functionality added to the architecture. A working proof of concept of the architecture is achieved by Hardware Description Language (HDL) based development and use of a Virtual Prototype of the architecture. The Virtual Prototype was used to evaluate the architecture functionality and performance in executing several newly developed example applications. Recommendations are made to further improve the system functionality.

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