Ces travaux de thèse traitent de la modélisation d’un interrupteur bipolaire commandable monolithique bidirectionnel en tension et en courant et s’inscrivent dans la gestion de l’énergie dans l’habitat. L’objectif est de concevoir un interrupteur à faible perte énergétique capable de s’intégrer au sein d’une électronique de commande intelligente.Ces travaux s’intéressent dans un premier temps aux différentes solutions existantes destinées à notre application. A travers cette étude, on présente ainsi les avantages et les inconvénients des interrupteurs discrets ou encore des solutions monolithiques. On s’intéresse ensuite à l’étude d’un transistor bipolaire de puissance symétrique vertical. A l’aide de simulations par éléments finis, une étude bidimensionnelle et statique a permis de valider sa fonctionnalité à savoir son aptitude à fonctionner sous le réseau alternatif domestique. L’étude se concentrera ensuite sur les différentes technologies destinées à l’améliorer. En optant pour des caissons fortement dopés judicieusement placés au niveau de la base, il est démontré que les performances d’un tel composant peuvent être augmentées grâce au phénomène d’autoblindage. Finalement, dans le but de simplifier la réalisation de cet interrupteur, la technologie du RESURF sur SOI a été retenue. La structure, latérale, a ensuite été étudiée grâce à des simulations statiques bidimensionnelles puis tridimensionnelles qui ont mis en valeur l’intérêt de cette technologie tant au niveau de la conception qu’au niveau de la réalisation de la structure. / This study deals with the modeling of a monolithic switch bidirectional in current and voltage with full turn-off control for household appliances. The goal is to design a low losses switch which can be integrated to smart electronics functions. These works are focused, first, on discrete and monolithic existing solutions designed for such appliances before pointing out their main advantages and drawbacks. Monolithic structures are preferred over discrete ones thanks to their easiness to be integrated among other structures on the same substrate. The study is focused then on a vertical and symmetrical power bipolar transistor. 2D static simulations in finite elements performed on the structure confirm its ability to work on the mains. Further studies underline the possibility to improve it. By implementing around the active base heavily doped caissons which create a shielding effect, one can increase the structure performances. Finally, to simplify the switch processing steps, SOI RESURF technology is chosen. The lateral structure is studied thanks to 2D and 3D simulations which emphasize the benefits of such technology on both its design and manufacturing process.

The effect of the electrical field enhancement at the junction discontinuities and its impact on the on-state resistance of power semiconductor devices was investigated. A systematic analysis of the mechanisms behind the techniques that can be used for the edge termination in power semiconductor devices was performed. The influence of the passivation layer properties, such as effective interface charge and dielectric permittivity, on the devices with different edge terminations was analyzed using numerical simulation. A compact analytical expression for the optimal JTE dose was proposed for the first time. This expression has been numerically evaluated for different targeted values of the blocking voltage and the maximum electric field, always resulting in the optimal field distribution that does not require further optimization with 2-D device simulator. A compact set of rules for the optimal design of super-junction power devices was developed. Compact analytical expressions for the optimal dopings and dimensions of the devices employed the field compensation technique are derived and validated with the results of numerical simulations on practical device structures. A comparative experimental study of several approaches used for the edge termination in SiC power diodes and transistors was performed. The investigated techniques included the mesa termination, high-k termination, JTE, and the combination of JTE and field plate edge termination. The mesa edge termination was found to be the most promising among the techniques investigated in this work. This stand-along technique satisfied all the imposed requirements for the ?ideal? edge termination: performance, reproducibility (scalability), and cost-efficiency. First of all, it resulted in the maximum one-dimensional electric field (E1DMAX) at the main device junction equal to 2.4 MV/cm or 93% of the theoretical value of critical electric field in 4H-SiC. Secondly, the measured E1DMAX was found to be independent of the voltage blocking layer parameters that demonstrate the scalability of this technique. Lastly, the implementation of this technique does not require expensive fabrication steps, and along with an efficient use of the die area results in the low cost and high yield.