The thesis deals with design and implementation of controllers for the RMAP protocol, which is used by SpaceWire network endpoints to access memory contents of another endpoint. The theoretical research introduces concepts of the SpaceWire network, then describes the RMAP protocol and the AMBA AHB bus interface in detail. The practical part of this thesis then uses this information to design and implement controllers for the RMAP protocol. It first defines an architecture of these controllers, then describes design of individual blocks based on this architecture. As a next step, the thesis describes methods used to verify designed controllers and to test these controllers in an FPGA chip. Finally, an analysis of maximum frequency and usage of FPGA resources is done based on estimates provided by the synthesis tool.

This work presents the advancements in the development of simulation models of spacecraft components as part of a testbench for verification of onboard flight software. The satellite and its mission are briefly described as to give an idea of the conditions where the simulation has to run. The simulation environment, SimTG, is also introduced and a description of the developed models is presented. The models required interaction between different simulation environments, real hardware and simulated hardware, and also some data processing was necessary in order to filter undesired information. Finally, the performance of the models was tested and verified and a sensible improvement of the state of the testbench on the simulation side was achieved, although a considerable amount of work still lies ahead before a complete onboard software verification tool is ready.