The increase in the number of cores that can be integrated on a single chip has forced the designer to use computer network concepts for design of System on Chip (SoC). This idea led to development of Network on Chip (NoC) to deal with more cores on a single chip. NoC has three main parts, namely routers, link and network interface through which cores are connected to NoC. Router is one of the most important parts because cores communicate with other cores through routers. One of the important tasks for a NoC designer is to design router with low latency.Router design depends on the routing protocol and routing algorithm used. Two kinds of routing algorithms are source routing and distributed routing. In source routing, complete route information is available in Head flit while in distributed routing, routing decisions are taken inside every router on the path. Source routing has speed advantage over distributed routing because the packet itself contains the routing information. But source routing leads to overhead to store complete path information in the header of each packet. To overcome this flaw, junction based source routing has been introduced. If destination is far away from the source then first packet will go to a junction and get the new path information from the junction to the destination. Thus we need to store the path information only for a few hops in the packet header. This idea has been taken from the daily experience of train journey. In this thesis we have developed design of a router for junction based source routing. Main component of simple router includes buffering, header modification and making route decision. Router includes a table called Path Table which stores information about paths from junction to various destinations. JB router also includes, picking up the new path information from Path Table and modify the header by adding new path information.We have developed VHDL designs of two versions of the routers for Junction Based Routing. The delay performance of routers have been analysed through simulation. A simple prototype of the router has also been implemented in Altera FPGA to find out the resource requirements of the new router designs.