This thesis investigates distributed router architectures and IP networks with centralized control. While the current trend in IP-router architectures is towards decentralized design, there have also been research proposals for centralizing the control functions in IP networks. With continuous evolution of routers and IP networks, we believe that eventually IP networks in an autonomous system (AS) and a distributed router might converge into one network system. This system, which can be considered both as a distributed router and a centrally-controlled IP network, is divided into a control plane and a forwarding plane. The control plane is responsible for routing, management and signalling protocols, while the forwarding plane is responsible for forwarding packets. The work in this thesis covers both the forwarding and control planes. In the forwarding plane, we study network processor systems that function as forwarding elements in a distributed router. We introduce a system model and a simulation tool based on the model. Using the simulation tool, we investigate network processor system design by studying throughput, utilization, queueing behavior and packet delays. In addition to network processor systems, we study IP-address lookup, which is one of the key packet processing functions in Internet routers. Our work in IP-address lookup contains an efficient lookup algorithm, a scheme to divide the lookup procedure into two-stages in a distributed router, and an approach to perform efficient lookup on a router supporting multiple virtual routers. In the control plane, we study three emerging research issues with centralized control. We provide a thorough study of the routing convergence process in networks with centralized control, and compare it with decentralized link-state routing protocols. We propose an efficient approach to perform traffic engineering and routing in networks with centralized control, and compare it with an approach using optimized link weights. Finally, we present an approach to perform loop-free updates of forwarding tables when the forwarding paths change. This loop-free update approach is particularly useful in networks with centralized control. The results presented in this thesis are useful for building next-generation routers and IP networks with centralized control that might eventually converge into one network system. / QC 20100726

The increase in the number of cores that can be integrated on a single chip has forced the designer to use computer network concepts for design of System on Chip (SoC). This idea led to development of Network on Chip (NoC) to deal with more cores on a single chip. NoC has three main parts, namely routers, link and network interface through which cores are connected to NoC. Router is one of the most important parts because cores communicate with other cores through routers. One of the important tasks for a NoC designer is to design router with low latency.Router design depends on the routing protocol and routing algorithm used. Two kinds of routing algorithms are source routing and distributed routing. In source routing, complete route information is available in Head flit while in distributed routing, routing decisions are taken inside every router on the path. Source routing has speed advantage over distributed routing because the packet itself contains the routing information. But source routing leads to overhead to store complete path information in the header of each packet. To overcome this flaw, junction based source routing has been introduced. If destination is far away from the source then first packet will go to a junction and get the new path information from the junction to the destination. Thus we need to store the path information only for a few hops in the packet header. This idea has been taken from the daily experience of train journey. In this thesis we have developed design of a router for junction based source routing. Main component of simple router includes buffering, header modification and making route decision. Router includes a table called Path Table which stores information about paths from junction to various destinations. JB router also includes, picking up the new path information from Path Table and modify the header by adding new path information.We have developed VHDL designs of two versions of the routers for Junction Based Routing. The delay performance of routers have been analysed through simulation. A simple prototype of the router has also been implemented in Altera FPGA to find out the resource requirements of the new router designs.