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ACCELERATING REAL-TIME SPACE DATA PACKET PROCESSINGDowling, Jason, Welling, John, Aerosys, Loral, Nanzetta, Kathy, Bennett, Toby, Shi, Jeff 11 1900 (has links)
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / NASA’s use of high bandwidth packetized Consultative Committee for Space Data
Systems (CCSDS) telemetry in future missions presents a great challenge to ground
data system developers. These missions, including the Earth Observing System
(EOS), call for high data rate interfaces and small packet sizes. Because each packet
requires a similar amount of protocol processing, high data rates and small packet
sizes dramatically increase the real-time workload on ground packet processing
systems.
NASA’s Goddard Space Flight Center has been developing packet processing
subsystems for more than twelve years. Implementations of these subsystems have
ranged from mini-computers to single-card VLSI multiprocessor subsystems. The
latter subsystem, known as the VLSI Packet Processor, was first deployed in 1991 for
use in support of the Solar Anomalous & Magnetospheric Particle Explorer
(SAMPEX) mission. An upgraded version of this VMEBus card, first deployed for
Space Station flight hardware verification, has demonstrated sustained throughput of
up to 50 Megabits per second and 15,000 packets per second. Future space missions
including EOS will require significantly higher data and packet rate performance. A
new approach to packet processing is under development that will not only increase
performance levels by at least a factor of six but also reduce subsystem replication
costs by a factor of five. This paper will discuss the development of a next generation
packet processing subsystem and the architectural changes necessary to achieve a
thirty-fold improvement in the performance/price of real-time packet processing.
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Cost Beneficial Solution for High Rate Data ProcessingMirchandani, Chandru, Fisher, David, Ghuman, Parminder 10 1900 (has links)
International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / GSFC in keeping with the tenets of NASA has been aggressively investigating new
technologies for spacecraft and ground communications and processing. The application
of these technologies, together with standardized telemetry formats, make it possible to
build systems that provide high-performance at low cost in a short development cycle.
The High Rate Telemetry Acquisition System (HRTAS) Prototype is one such effort that
has validated Goddard's push towards faster, better and cheaper. The HRTAS system
architecture is based on the Peripheral Component Interconnect (PCI) bus and VLSI
Application-Specific Integrated Circuits (ASICs). These ASICs perform frame
synchronization, bit-transition density decoding, cyclic redundancy code (CRC) error
checking, Reed-Solomon error detection/correction, data unit sorting, packet extraction,
annotation and other service processing. This processing in performed at rates of up to
and greater than 150 Mbps sustained using a high-end performance workstation running
standard UNIX O/S, (DEC 4100 with DEC UNIX or better). ASICs are also used for the
digital reception of Intermediate Frequency (IF) telemetry as well as the spacecraft
command interface for commands and data simulations.
To improve the efficiency of the back-end processing, the level zero processing sorting
element is being developed. This will provide a complete hardware solution to extracting
and sorting source data units and making these available in separate files on a remote disk
system. Research is on going to extend this development to higher levels of the science
data processing pipeline. The fact that level 1 and higher processing is instrument
dependent; an acceleration approach utilizing ASICs is not feasible. The advent of field
programmable gate array (FPGA) based computing, referred to as adaptive or reconfigurable computing, provides a processing performance close to ASIC levels while
maintaining much of the programmability of traditional microprocessor based systems.
This adaptive computing paradigm has been successfully demonstrated and its cost
performance validated, to make it a viable technology for the level one and higher
processing element for the HRTAS.
Higher levels of processing are defined as the extraction of useful information from
source telemetry data. This information has to be made available to the science data user
in a very short period of time. This paper will describe this low cost solution for high rate
data processing at level one and higher processing levels. The paper will further discuss
the cost-benefit of this technology in terms of cost, schedule, reliability and performance.
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