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This thesis focuses on the design and analysis of an optimal filter that is capable of making one-step-ahead prediction of a bandlimited signal while attenuating unwanted noise. First, the filter optimization based on the least mean-square-error criterion is presented. Then, an exact expression for the achievable minimum mean square error (MMSE) is derived with the aid of the Toeplitz form method and Szego theory. Based on this MMSE expression, the formulae for estimating the optimal filter¡¦s in-band prediction error and out-of-band noise attenuation are derived. Finally, the optimal filter is applied to sigma-delta modulation. It shows that the modulation performance and stability are intimately related to the filter performance and can be accurately estimated by the derived formulae.

A new low power, wideband wireless transmitter able to convert any RF signal into a constant envelope signal enabling the use of a nonlinear and efficient power amplifier is presented. In the transmitter architecture, two normalized phase signals and the envelope are separated and processed separately. A 1-bit 2nd order SD modulator codes the envelope. Quantization noise is attenuated by a S&H interpolator introducing notches at multiples of the sampling frequency. Phase and Envelope signals are recombined and upconverted directly to radio frequencies using a novel full-digital, wideband quadrature modulator. This mixer takes advantage of the 1-bit SD output. As both LOs and envelope signals are represented by two-level signals, the product of these signals (XOR function) leads to a two-level signal, which can be used as command signal in the multiplexors. Phase signals or theirs complements that are generated by a simple Inversion Block are passed through this multiplexor at the rate of driving signals. This enables to implement a high frequency, wideband mixer instead of a more complex three-input modulator. This IQ mixer is very simple to implementate as it uses only CMOS logic gates. The generation of the quadrature clock signals in the mixer is obtained by carefully design of two paths to avoid mismatch to assure an error less than 1º (only demonstrated in simulation) and the use of SR flipflops to generate correctly the complementary signal prior to the divide-by-two circuit. Two asynchronous 9-bit DACs eliminate the 10-bit high-speed digital adder at the output of the IQ modulator and the 10-bit DAC before the PA, saving power and relaxing adder design constraints. Each DAC is divided into two full binary-weighted DACs of 4 and 5 bits. This topology enables to reduce the size ratios between the most and least significant bits related to a classic 9-bit binary-weighted structure (16 instead of 256). To test the speed and the gain control of the standalone DAC over 45 dB, a prototype DAC is designed in 0.13 ;m BiCMOS technology from STMicroelectronics together with a 1.4 GHz 9-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Over the output power range, measurements show a SFDR>25 dB with a power dissipation of 25 mW at the maximum differential output power of -3 dBm (RL=50 @). The whole transmitter is designed and implemented and a prototype transmitter is built in 0.13 μm BiCMOS STMicroelectronics process. This low cost single chip digital radio transmitter demonstrates a data rate of 1.8 GHz. The image level is measured to be -12 dBc at this sampling frequency. Dynamic range in the transmitter is 35 dB for sampling frequencies lower than 800 MHz and 25 dB for higher sampling frequencies up to 1.8 GHz. For a two-tone signal, the maximum single-ended output power is -31dBm for each tone and the power dissipation is about 35 mW. This architecture enables flexible and software-defined transmitter. Sampling frequency in the SD coder can be varied to adapt to different communications standards in terms of in-band and outof-band noise requirements and variable LO frequencies can be used. Moreover, the transmitter can adapt dynamically the output power to the power amplifier depending of the required transmitted power at the output of the PA. The transmitter has demonstrated its potential for use as a universal transmitter for applications targeting any frequency band and modulation schema up to 900 MHz (carrier frequency) and occupies a die area of 300x320 ;m2. The generated differential signal can be easily amplified by a switched-mode Power Amplifier (PA) in an efficient way because it presents constant-envelope and the PA can work in the saturation zone, which represents its optimal operation point.

Due to the rapid growth of the communication market, a large amount of research is in process toward a high speed and high resolution sigma-delta A/D converter. This dissertation focuses on the design of a single-stage sigma-delta A/D converter with very low oversampling ratio for the wireless application. An architecture for a multibit single-stage delta-sigma A/D converter with two-step quantization is proposed. Both the MSB and LSB signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine DEM and DAC is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise-shaped by using a digital requantization (REQ) algorithm. A second-order single-stage sigma-delta A/D converter with 8-bit two-step inner quantization is proposed in this dissertation, which employs the feed-forward branches to reduce the integrator output swing. The proposed modulator is implemented with TSMC 0.25 μm mixed-signal process, using the switched-capacitor circuit. The measured system achieves the dynamic range of 70 dB under an oversampling ratio of 16 with the REQ algorithm reducing the noise floor in the signal bandwidth by 20 dB.

Short Word-Length refers to single-bit, two-bit or ternary processing systems. SWL systems use Sigma-Delta Modulation (SDM) technique to express an analogue or multi-bit input signal in terms of a high frequency single-bit stream. In Sigma-Delta Modulation, the input signal is coarsely quantized into a single-bit representation by sampling it at a much higher rate than twice the maximum input frequency viz. the Nyquist rate. This single-bit representation is almost exclusively filtered to remove conversion quantization noise and sample decimated to the Nyquist frequency in preparation for traditional signal processing. SWL algorithms have a huge potential in a variety of applications as they offer many advantages as compared to multi-bit approaches. Features of SWL include efficient hardware implementation, increased flexibility and massive cost savings. Field Programmable Gate Arrays (FPGAs) are SRAM/FLASH based integrated circuits that can be programmed and re-programmed by the end user. FPGAs are made up of arrays of logic gates, routing channels and I/O blocks. State-of-the-art FPGAs include features such as Advanced Clock Management, Dedicated Multipliers, DSP Slices, High Speed I/O and Embedded Microprocessors. A System-on-Programmable-Chip (SoPC) design approach uses some or all the aforementioned resources to create a complete processing system on the device itself, ensuring maximum silicon area utilization and higher speed by eliminating inter-chip communication overheads. This dissertation focuses on the application of SWL processing systems in audio Class-D Amplifiers and aims to prove the claims of efficient hardware implementation and higher speeds of operation. The analog Class-D Amplifier is analyzed and an SWL equivalent of the system is derived by replacing the analogue components with DSP functions wherever possible. The SWL Class-D Amplifier is implemented on an FPGA, the standard emulation platform, using VHSIC Hardware Description Languages (VHDL). The approach is taken a step forward by adding re-configurability and media selectivity and proposing SDM adaptivity to improve performance.

<p> </p><p>I detta examensarbete har metoder för design av en FPGA-baserad PCM-till-PWM-modulator för klass D-audioförstärkare testats och utvärderats. Rapporten diskuterar med stöd av matematisk analys och simuleringar interpoleringsmetoder, pulsbreddsmodulering, samplingsprocesser och sigma-delta-modulatorer. Den föreslagna designen bygger på uppsampling, förkompensering, brusformning och pulsbreddsmodulering. Designens prestanda har verifierats genom simulering av modell och implementering i hårdvara.</p><p> </p> / <p> </p><p>This thesis experiments and evaluates methods for design of an FPGA based PCM-to-PWM modulator to be used in a class D audio amplifier. By utilizing mathematical analysis and simulations interpolation methods, pulse width modulation, cross point derivers and sigma delta modulators are discussed. The proposed design consists of upsampling, predistortion, noise shaping and pulse width modulation. The design has been validated through model based simulation and implementation in hardware.</p><p> </p>

The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative. / QC 20120528

I detta examensarbete har metoder för design av en FPGA-baserad PCM-till-PWM-modulator för klass D-audioförstärkare testats och utvärderats. Rapporten diskuterar med stöd av matematisk analys och simuleringar interpoleringsmetoder, pulsbreddsmodulering, samplingsprocesser och sigma-delta-modulatorer. Den föreslagna designen bygger på uppsampling, förkompensering, brusformning och pulsbreddsmodulering. Designens prestanda har verifierats genom simulering av modell och implementering i hårdvara. / This thesis experiments and evaluates methods for design of an FPGA based PCM-to-PWM modulator to be used in a class D audio amplifier. By utilizing mathematical analysis and simulations interpolation methods, pulse width modulation, cross point derivers and sigma delta modulators are discussed. The proposed design consists of upsampling, predistortion, noise shaping and pulse width modulation. The design has been validated through model based simulation and implementation in hardware.

This thesis presents a novel three-level modulation technique for a Class-D audio amplifier, attempting to improve the poor performance of the conventional two-level modulation scheme at low input levels. The main drawback of the conventional two-level PWM (pulse-width modulation) and SDM (sigma-delta modulation) Class-D amplifier is that, with a zero input or small input, the excessively fast switching action at the output causes unwanted switching loss and switching noise, resulting in unnecessary energy waste and SNDR degradation. The presented three-level modulation circuit mainly consists of a linear feedback compensator, two comparators, and a switching logic circuit. The simulation and experimental results shows that the proposed three-level modulation s cheme outperforms the two-level sigma-delta modulation scheme in both efficiency and performance.

MEMS accelerometers are quickly approaching navigation grade performance and navigation market for MEMS accelerometer systems are expected to grow in the recent years. Compared to conventional accelerometers, these micromachined sensors are smaller and more durable but are generally worse in terms of noise and dynamic range performance. Since MEMS accelerometers are already dominant in the tactical and consumer electronics market, as they are in all modern smart phones today, there is significant demand for MEMS accelerometers that can reach navigation grade performance without significantly altering the developed process technologies. This research aims to improve the performance of previously fabricated and well-known MEMS capacitive closed loop &Sigma / &Delta / accelerometer systems to navigation grade performance levels. This goal will be achieved by reducing accelerometer noise level through significant changes in the system architecture and implementation of a new electronic interface readout ASIC. A flexible fourth order &Sigma / &Delta / modulator was chosen as the implementation of the electro-mechanical closed loop system, and the burden of noise shaping in the modulator was shifted from the mechanical sensor to the programmable electronic readout. A novel operational transconductance amplifier (OTA) was also designed for circuit implementation of the electronic interface readout. Design and fabrication of the readout was done in a standard 0.35 &micro / m CMOS technology. With the newly designed and fabricated readout, single-axis accelerometers were implemented and tested for performance levels in 1g range. The implemented system achieves 5.95 &micro / g/sqrt Hz, 6.4 &micro / g bias drift, 131.7 dB dynamic range and up to 37.2 g full scale range with previously fabricated dissolved epitaxial wafer process (DEWP) accelerometers in METU MEMS facilities. Compared to a previous implementation with the same accelerometer element reporting 153 &micro / g/sqrtHz, 50 &micro / g bias drift, 106.8 dB dynamic range and 33.5 g full scale range / this research reports a 25 fold improvement in noise, 24 dB improvement in dynamic range and removal of the deadzone region.