Due to the lack of feedback networks, digital class D amplifiers operating in open loop typically have inferior performance when compared to analog class D amplifiers in closed loop configuration. This thesis presents an integrated distortion suppression circuit design for digital class D amplifiers, which forms a feedback loop around the output stage. This circuit suppresses the output stage distortion and noise by equalizing the modulator effective duty ratio and the output stage effective duty ratio. The suppression circuit is integrated with the class D modulator. An integrated class D amplifier output stage is implemented separately using a 0.35μm HV-CMOS technology. Experimental results confirm that the closed loop PSRR is improved by 15dB. The THD+N value is reduced by a factor of 2 to 30. The minimum THD+N is 0.03%, which is among the state of the art class D amplifiers.

Due to the lack of feedback networks, digital class D amplifiers operating in open loop typically have inferior performance when compared to analog class D amplifiers in closed loop configuration. This thesis presents an integrated distortion suppression circuit design for digital class D amplifiers, which forms a feedback loop around the output stage. This circuit suppresses the output stage distortion and noise by equalizing the modulator effective duty ratio and the output stage effective duty ratio. The suppression circuit is integrated with the class D modulator. An integrated class D amplifier output stage is implemented separately using a 0.35μm HV-CMOS technology. Experimental results confirm that the closed loop PSRR is improved by 15dB. The THD+N value is reduced by a factor of 2 to 30. The minimum THD+N is 0.03%, which is among the state of the art class D amplifiers.

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In this thesis, the applicability of Class-D amplifiers to integrated wide-band communication line driver applications is studied. While Class-D techniques can address some of the efficiency limitations of linear amplifier structures and have shown promising results in low frequency applications, the low frequency techniques and knowledge need further development in order to improve their practicality for wide band systems. New structures and techniques to extend the application of Class-D to wide-band communication systems, in particular the HomePlug AV wire- line communication standard, will be proposed. Additionally, the digital processing requirements of these wide-band systems drives rapid movement towards nanometer technology nodes and presents new challenges which will be addressed, and new opportunities which will be exploited, for wide-band integrated Class-D line drivers. There are three main contributions of this research. First, a model of Class-D efficiency degradation mechanisms is created, which allows the impact of high-level design choices such as supply voltage, process technology and operating frequency to be assessed. The outcome of this section is a strategy for pushing the high efficiency of Class-D to wide band communication applications, with switching frequencies up to many hundreds of Megahertz. A second part of this research considers the design of efficient, fast and high power Class-D output stages, as these are the major efficiency and bandwidth bottleneck in wide-band applications. A novel NMOS-only totem pole output stage with a fast, integrated drive structure will be proposed. In a third section, a complete wide-band Class-D line driver is designed in a 0.13μm digital CMOS process. The line driver is systematically designed using a rigorous development methodology and the aims are to maximise the achievable signal bandwidth while minimising power dissipation. Novel circuits and circuit structures are proposed as part of this section and the resulting fabricated Class-D line driver test chip shows an efficiency of 15% while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected power.

Class D power amplifier applies in high efficiency circuit. In hearing aid system, we require high power efficiency, low-voltage and low-power. The operation of frequency is low frequency. All the circuits are designed based on the TSMC 035 CMOS process technology. The supply voltage is 1.5V and the input signal is 4KHz. Simulation results show that the Class D power efficiency is high efficiency amplifier. When 0.3V of 2KHz input signal is applied, The maximum THD is 0.63% and static current is 4uA and the efficiency is 83.6%.

The design of a low distortion and high efficiency self-oscillating power amplifier is presented. It is designed using TSMC 0.35µm, 2p4m CMOS technology. We use noise shaping to reduce the THD (Total Harmonic Distortion). This design can be applied to hearing aids. The supply voltage is 1.5V for hearing aids. Experimental results demonstrate that the proposed amplifier has the total harmonic distortion (THD) of 0.0751% and power efficiency around 90.1%. Measurement result reveals that this circuit can be up to 0.25% of the THD and 89.7% of the power efficiency. This result shows that the proposed power amplifier has superior performance in THD and power efficiency, and this circuit is applicable to low-distortion, high-efficiency, and low-voltage applications, such as the hearing aids.

The primary advantage of Class D amplifier is high power efficiency (typically >90%). However, there are two problems in open-loop Class D design: Total Harmonic Distortion (THD) and output dc static current (the power efficiency will be degraded). The THD is rising from non-ideal sample carrier in Pulse Width Modulation circuit, and output dc static current is due to the non-match transfer characteristic in output stage. For designer to have such problems will be a large load. To improve these two problems, we proposed a Class D power amplifier with passive feedback design. Simulation and Measurement results show that the power efficiency is higher than 90% at 250Hz ~ 4KHz. Furthermore, the THD is less than 0.24% at 4 KHz in both simulation and experimental results.

Les convertisseurs de puissance sont largement utilisés de nos jours dans des applications qui demandent une grande autonomie énergétique, comme par exemple ceux qui sont alimentés par des batteries. En particulier, les amplificateurs de type Class-D sont fréquemment utilisés dans les applications audio. Ces amplificateurs commutés ont une architecture ressemblante à celle d'un convertisseur DC-DC, ce qui les permet d'avoir une efficacité énergétique élevée. Cependant, leur inconvénient majeur est la forte émission en perturbations électromagnétiques (EM). Cela peut causer des problèmes de conformité avec les normes de compatibilité électromagnétique (CEM), ou bien perturbé le bon fonctionnement des applications électroniques qui l'entour. Pour cela, ils existent de nombreuses études qui permettent de réduire les émissions d'un amplificateur de Class D. Cependant, cela n'est pas suffisant pour retirer le filtre de CEM. Il est donc nécessaire d'optimiser ces filtres et de faciliter leurs conceptions. Ceci est le but de la présente thèse et il est divisé en quatre grandes parties. La première partie commence par développer une technique de modélisation dans le domaine fréquentiel. Cette technique qui est basée sur la détermination et la manipulation des matrices d'impédances a comme but de simuler et prédire les perturbations EM générées par un amplificateur de Class D. Tous les aspects théoriques de la méthode ont été développés. Ensuite, une application pratique sur un système de Class D dédié à la téléphonie mobile nous a permis de valider la méthode jusqu'à une fréquence de 100 MHz. Un amplificateur de Class D est une source de perturbation aussi bien sur les rails d'alimentation que sur les rails de sortie. Pour cela, le filtre de CEM est nécessaire sur les rails de l'alimentation comme il y est en sortie. Néanmoins, un filtre correctement construit doit être conçu en prenant en compte l'impédance de la charge qui est la batterie dans ce cas. Pour cela, la deuxième partie a pour objectif la mesure de l'impédance de la batterie sur la gamme de fréquence considérée. Ainsi, une technique de mesure d'impédance de batterie en utilisant un impédance mètre est développée. Ensuite, une application expérimentale sur un convertisseur DC-DC et une batterie nous a permis de valider la procédure de mesure. La troisième partie s'est focalisée sur l'optimisation du filtre de CEM. Le modèle fréquentiel développé dans la première partie est intégré dans une boucle d'optimisation basée sur un algorithme génétique. L'optimisation inclus plusieurs critères dans sa fonction objective qui sont l'augmentation de la capacité du filtre à réduire les émissions EM, la diminution des pertes supplémentaires due à l'utilisation du filtre et finalement le gain du filtre dans la bande de fréquence du signal audio. Cette étude est poursuivie par une validation expérimentale. La quatrième et la dernière partie étudie et quantifie les impacts du filtre de CEM sur la qualité audio de l'amplificateur. En effet, le filtre de CEM est l'un des chemins propagation du signal audio. Par suite, tout comportement non linéaire du filtre conduit à la distorsion du signal audio. Pour cela, cette partie est dédiée à la modélisation et la simulation des composants passifs contenant un matériau magnétique. En particulier, l'étude s'est focalisée sur la modélisation des perles de ferrite en utilisant le modèle de matériaux magnétiques Jiles-Aterthon. Les résultats de simulations sont comparés avec la mesure dans le domaine temporel et fréquentiel. En plus, le calcul du taux de distorsion harmonique nous a permis de valider le modèle sur une large plage d'amplitude. / Switching power management circuits are widely used in battery powered embedded applications in order to increase their autonomy. In particular, for audio applications, Class-D amplifiers are a widespread industrial solution. These, have a similar architecture of a buck converter but having the audio signal as reference. The switching nature of these devices allows us to increase significantly the power efficiency compared to linear audio amplifiers without reducing the audio quality. However, because of the switching behavior, Class-D amplifiers have high levels of electromagnetic (EM) emissions which can disturb the surrounding electronics or might not comply with electromagnetic compatibility (EMC) standards. To overcome this problem much architecture appeared in the state of the art that reduces the emissions, however, this has never been enough to remove electromagnetic interference (EMI) filters. It is then useful to optimize these filters, thus, it has been set as the goal of this PhD thesis. The latter has been divided to four main axes which can be resumed by the following. First, this work started by developing a frequency domain modeling method in order to simulate and predict the EMI of Class-D amplifiers in the final application. The method is based on system to block decomposition and impedance matrix modeling and manipulation. After providing all the theoretical background, the method has been validated on integrated differential Class-D amplifier. The experimental measurements have permitted to validate the method only up to 100MHz. However, this is sufficient to cover the conducted EMC frequency band. Second, the EMI at the supply rails of Class-D amplifiers has been treated. As the battery is often the same power supply for all applications in an embedded system, an EMI filter or a decoupling capacitor is needed to prevent the noise coupling by common impedance. Designing this filter needs the knowledge of the battery impedance at the desired frequencies. Therefore the present work dealt also with measuring the high frequency impedance of a battery. Afterwards, an experimental validation has been carried on with a DC-DC converter and a Class-D amplifier. The developed model allows a virtual test of the switching device in the final application. However, it is more useful if the model is able to help the system integrator in designing filters. Thus, third, the model has been implemented in an optimization loop based on a genetic algorithm in order to optimize the filter response, and also, reduce the additional power losses introduced by an EMI filter. The optimization search space has been limited to the components available on the market and the optimization result is given as component references of the optimal filter referring to the optimal solution found. This procedure has been validated experimentally. Finally, EMI filters often are constituted by magnetic components such as ferrite beads or inductors with magnetic cores. Thus, introducing the EMI filter in the audio path, adds a nonlinear behavior in the audio frequency band. Designing a high quality EMI filter require taking into account this phenomenon and studying its impact of the original amplifier audio performance. Therefore, the Jiles-Atherton model for magnetic materials has been used for ferrite bead modeling. Hereafter, the impact on the time and frequency domain signals has been simulated and compared to measurements. Finally, the total harmonic distortion (THD) has been computed for different signal amplitudes and compared to the THD measured using an audio analyzer. Accurate results have been obtained on a wide range of signal amplitudes. As a conclusion, this work aimed to design optimal EMI filters for Class-D amplifiers. Thus, we dealt with improving their EMI response, reducing their additional power losses and evaluating their impact on the audio quality.

Thesis (MScEng)--Stellenbosch University, 2012 / ENGLISH ABSTRACT: The class-D audio power amplifier has found widespread use in both the consumer and professional audio industry for one reason: efficiency. A higher efficiency leads to a smaller and cheaper design, and in the case of mobile devices, a longer battery life. Unfortunately, the basic class-D amplifier has some serious drawbacks. These include high distortion levels, a load dependent frequency response and the potential to radiate EMI. Except for EMI, the aforementioned issues can be mitigated by the proper implementation of global negative feedback. Negative feedback also has the potential to indirectly reduce EMI, since the timing requirements of the output devices can be relaxed. This thesis discusses the design of a clocked analogue controlled pulse-width modulated class-D audio amplifier with global negative feedback. The analogue control loop is converted to the z-domain by modelling the PWM comparator as a sampling operation. A method is implemented that improves clip recovery and ensures stability during over-modulation. Loop gain is shaped to provide a high gain across the audio band, and ripple compensation is implemented to minimize the negative effect of ripple feedback. Experimental results are presented. / AFRIKAANSE OPSOMMING: Die klas-D klankversterker geniet wydverspreide gebruik in beide die verbruiker en professionele oudio industrie vir een rede: benuttingsgraad. ’n Hoër benuttingsgraad lei tot ’n kleiner en goedkoper ontwerp, en in die geval van draagbare toestelle, tot langer batterylewe. Ongelukkig het die basiese klas-D klankversterker ernstige tekortkominge, naamlik hoë distorsievlakke, ’n lasafhanklike frekwensierespons en die vermoë om EMI te genereer. Behalwe vir EMI kan hierdie kwessies deur die korrekte toepassing van globale negatiewe terugvoer aangespreek word. Negatiewe terugvoer het ook die potensiaal om EMI indirek te verminder, aangesien die tydvereistes van die skakel stadium verlaag kan word. Hierdie tesis bespreek die ontwerp van ’n geklokte analoog-beheerde pulswydte-modulerende klas-D klankversterker met globale negatiewe terugvoer. Die analoogbeheerlus word omgeskakel na die z-vlak deur die PWM vlakvergelyker as ’n monster operasie te modelleer. ’n Metode word geïmplementeer wat die stabiliteit van die lus verseker tydens oormodulasie. Die lusaanwins word gevorm om ’n hoë aanwins in die oudioband te verseker en riffelkompensasie word geïmplementeer om die negatiewe effek van terugvoerriffel teen te werk. Eksperimentele resultate word voorgelê.

Synthetic aperture sonar (SAS) is a wide-beam sonar technique commonly used for mapping the seafloor at high resolution. The Acoustics Research Group at the University of Canterbury operates a towed SAS system known as KiwiSAS-IV. This is currently being redesigned with the aim of reducing the weight, size and power requirements of the system. The long term goal is to make it capable of being mounted on an autonomous underwater vehicle (AUV) so that mapping of remote and/or dangerous waters can be accomplished without human interaction. This thesis presents the design of the front-end electronics used to drive the 36 transducers to produce the acoustic beam and receive the returning signals after they have reflected off a target. To achieve sufficient range, the transducers are driven with a 200 Vₚ₋ₚ signal with a maximum frequency of 110 kHz. This design uses class D switching amplifiers to generate these waveforms. The AD9271 integrated circuit, which can handle eight transducers simultaneously, is used to amplify the incoming signals and sample them at up to 50 MHz. This high sampling rate multiplied by all 36 transducers results in an amount of data which is too great for a conventional microprocessor-based system to handle. Instead, an FPGA is used to receive this data, decimate it using multiplier-free cascaded integrator-comb (CIC) filters, and then pass it to the back-end system for further processing and storage. A prototype circuit was created to test the theory developed in this thesis. This showed that the system is capable of generating the necessary waveforms and amplifying, capturing, and decimating the returning signals. However, further refinement is required before it is able to be used in the sonar system.