No description available.

The sigma-delta modulator is a popular signal amplitude quantization error (or noise) shaper used in oversampling analogue-to-digital and digital-to-analogue converter systems. The shaping of the noise frequency spectrum is performed by feeding back the quantization errors through a time delay element filter and feedback loop in the circuit, and by the addition of a possible stochastic dither signal at the quantizer. The aim in audio systems is to limit audible noise and distortions in the reconverted analogue signal. The formulation of the sigma-delta modulator as a discrete dynamical system provides a useful framework for the mathematical analysis of such a complex nonlinear system, as well as a unifying basis from which to consider other systems, from pseudorandom number generators to stochastic resonance processes, that yield equivalent formulations. The study of chaos and other complementary aspects of internal dynamical behaviour in previous research has left important issues unresolved. Advancement of this study is naturally facilitated by the dynamical systems approach. In this thesis, the general order feedback/feedforward sigma-delta modulator with multi-bit quantizer (no overload) and general input, is modelled and studied mathematically as a dynamical system. This study employs pertinent topological methods and relationships, which follow centrally from the symmetry of the circle map interpretation of the error state space dynamcis. The main approach taken is to reduce the nonlinear system into local or special case linear systems. Systems of sufficient structure are shown to often possess structured random, or random-like behaviour. An adaptation of Devaney's definition of chaos is applied to the model, and an extensive investigation of the conditions under which the associated chaos conditions hold or do not hold is carried out. This seeks, in part, to address the unresolved research issues. Chaos is shown to hold if all zeros of the noise transfer function lie outside the unit circle of radius two, provided the input is either periodic or persistently random (mod delta). When the filter satisfies a certain continuity condition, the conditions for chaos are extended, and more clear cut classifications emerge. Other specific chaos classifications are established. A study of the statistical properties of the error in dithered quantizers and sigma-delta modulators is pursued using the same state space model. A general treatment of the steady state error probability distribution is introduced, and results for predicting uniform steady state errors under various conditions are found. The uniformity results are applied to RPDF dithered systems to give conditions for a steady state error variance of delta squared over six. Numerical simulations support predictions of the analysis for the first-order case with constant input. An analysis of conditions on the model to obtain bounded internal stability or instability is conducted. The overall investigation of this thesis provides a theoretical approach upon which to orient future work, and initial steps of inquiry that can be advanced more extensively in the future.

" Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) bio-potential signals are commonly recorded in clinical practice. Typically, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and can affect the diagnosis of illness. Therefore, there is a great demand for low-power, small-size, and ambulatory bio-potential signal acquisition systems. Recent work on instrumentation amplifier design for bio-potential signals can be broadly classified as using one or both of two popular techniques: In the first, an AC-coupled signal path with a MOS-Bipolar pseudo resistor is used to obtain a low-frequency cutoff that passes the signal of interest while rejecting large dc offsets. In the second, a chopper stabilization technique is designed to reduce 1/f noise at low frequencies. However, both of these existing techniques lack control of low-frequency cutoff. This thesis presents the design of a mixed- signal integrated circuit (IC) prototype to provide complete, programmable analog signal conditioning and analog-to-digital conversion of an electrophysiologic signal. A front-end amplifier is designed with low input referred noise of 1 uVrms, and common mode rejection ratio 102 dB. A novel second order sigma-delta analog- to-digital converter (ADC) with a feedback integrator from the sigma-delta output is presented to program the low-frequency cutoff, and to enable wide input common mode range of ¡Ãƒâ€œ0.3 V. The overall system is implemented in Jazz Semiconductor 0.18 um CMOS technology with power consumption 5.8 mW from ¡Ãƒâ€œ0.9V power supplies. "

This thesis focuses on the design and analysis of an optimal filter that is capable of making one-step-ahead prediction of a bandlimited signal while attenuating unwanted noise. First, the filter optimization based on the least mean-square-error criterion is presented. Then, an exact expression for the achievable minimum mean square error (MMSE) is derived with the aid of the Toeplitz form method and Szego theory. Based on this MMSE expression, the formulae for estimating the optimal filter¡¦s in-band prediction error and out-of-band noise attenuation are derived. Finally, the optimal filter is applied to sigma-delta modulation. It shows that the modulation performance and stability are intimately related to the filter performance and can be accurately estimated by the derived formulae.

Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ± 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V supply.

The thesis focuses on a higher order noise-shaping Δ ADC architecture which employs filtered quantization error as a dither signal. Furthermore, the work studies implementation challenges using Switched-Capacitor and Switched-Current techniques. Digitization in an IF conversion receiver can be accomplished either with a wide band Nyquist rate ADC or a BandPass Δ ADC. The use of the latter is the optimum solution since the bandwidth of the IF signals is typically much smaller than the carrier frequency and reducing the quantization noise in the entire nyquist band becomes superfluous. Instead by using BandPass Δ ADCs the quantization noise power is reduced only in a narrow band around IF location. We study state-of-the-art high dynamic range Δ data converter topologies suited for wide-band radio receivers. We propose a topology which achieves higher order noise shaping by employing filtered quantization error as a dither signal. We study implementation challenges for Δ converters in digital technology. Traditionally, Δ ADCs used Switched-Capacitor (SC) circuits to realize their building blocks. This analog sample-data technique is based on the idea that a periodically switched capacitor can emulate a resistor. The limiting factor that degrades the performance of SC circuits implemented in standard VLSI technologies is the continuous reduction of supply voltages, prompted by the continuous scaling-down process. This fact, which is advantageous for digital circuitry, makes the design of SC circuits difficult, which are forced to use clock boosting strategies for switches and to increase the power consumption in order to obtain high-speed and high dynamic range opamps with low voltage operation. In this scenario, the use of current-domain sampled data technique, also named Switched-Current (SI), instead of voltages results advantageous for several reasons. As the signal carriers are currents, the supply voltage does not limit the signal range as much as in SC circuits. Therefore, SI circuits are more suitable than SC for low-voltage operation. This work studies the feasibility and bottlenecks of implementing Δ modulator building blocks using SI technique. A BandPass filter, DAC and 1-bit quantizer have been designed in 0.18µm technology using SI technique. (For mathematical equations pl refer the pdf file)

Zugl.: Dresden, Techn. Univ., Diss., 2007

No description available.

Wireless sensor nodes are emerging in a wide range of critical applications such as environmental monitoring, health applications, home automation and military surveillance and reconnaissance. The addition of low power wireless capability to such sensor nodes allows communication between a node and a base station or between nodes, resulting in the formation of wireless sensor networks. Sensor networks can use the information available from the distributed sensor nodes to determine the location and nature of a stimulus or environmental condition. The information collected by the base station can be used to determine the appropriate course of action for dealing with the stimulus. In chemical/biological defense or safety monitoring scenarios, wireless sensor networks can be used to identify and track harmful chemical or biological agents which might be present in a particular area. Due to the potentially remote areas that wireless sensor networks aim to cover, it is essential to minimize the power consumption of a sensor node so that it can operate over a long period of time without a connection to the power grid. Sensor nodes can contain multiple blocks, such as the readout circuit which interfaces with the sensor, an embedded processor, and the wireless transceiver circuits, all of which need to operate on a low power budget. This thesis specifically focuses on design of low power mixed signal readout circuits which interface with chemoresistive chemical sensors, i.e. sensors that demonstrate a variation of resistance (or impedance) in the presence of chemical agents. For this thesis, the sensor can be either a chemoresistive bead or a nanowire. By integrating multiple non-specific chemoresistive sensors together in arrays, a cross-reactive array can be realized, where the combined response of the arrayed sensors can be used to determine analytes present in a mixture even if their concentrations are low. In this thesis, a CMOS resistive readout circuit based on a sigma-delta ADC is presented. The design is used to measure the resistance of chemoresistive beads and nanowires with respect to time. The frequency of the ADC output varies as the resistance of a sensor changes and, based on the magnitude and duration of the variation, the type of chemical agent and its concentration can potentially be estimated. For future cross-reactive sensor applications, an array of 16x16 sites is also included in the readout circuit design. Individual sites in the sensor array can be accessed using addressing blocks which designed to select a particular row and column using an 8-bit addressing system. This thesis also covers the techniques used for integration of chemoresistive beads and nanowires into the array locations provided on the prefabricated CMOS IC. Measurement results that demonstrate the operation of the resistive readout circuitry are presented. Finally, a second readout circuit is proposed to measure complex impedance variations of a sensor device. Measurement of magnitude and phase changes of a sensor device can provide another degree of freedom in the analysis of chemical mixture. Simulation results demonstrating the functionality of the proposed impedance measurement system are also presented. / Master of Science

Design step for Sigma-Delta ADC is introduced. Suitable solution for performance improvement of the original Sigma-Delta ADC, which meets new requirements on resolution of 16 bits and signal bandwidth 20-50 kHz is presented. Advantage of using multi-bit quantization and DEM DWA method reducing the linearity requirements of the internal feedback DAC is shown.