University, Diss., 2002--Essen.

Zugl.: Ilmenau, Techn. Univ., Diplomarbeit, 2008

Zugl.: Siegen, Univ., Diss., 2007

Chemnitz, Techn. Univ., Diplomarb., 2004.

Techn. Hochsch., Diss., 2001--Aachen.

Universiẗat, Diss., 2003--Dortmund.

Techn. Universiẗat, Diss., 2003--Berlin.

This diploma thesis discusses the implementation of a GCC target for the Texas Instruments TMS320C6000 DSP platform. To this end, it makes use of mechanisms offered by GCC for porting to new target architectures. GCC internals such as the handling of conditional jumps and the layout of stack frames are investigated and applied to the new architecture. / Diese Diplomarbeit behandelt die Implementierung eines GCC-Targets für die DSP-Plattform TMS320C6000 von Texas Instruments. Dazu werden Mechanismen genutzt, die GCC für die Portierung auf neue Zielplattformen anbietet. GCC-Interna, wie die Behandlung bedingter Sprünge und das Layout von Stack-Frames, werden untersucht und auf die neue Architektur angewendet.

This diploma thesis discusses the applicability of GCC optimization algorithms for the TI TMS320C6x processor family. Conditional and Parallel Execution is used to speed up the resulting code. It describes the optimization framework of the GCC version 4.0 and the implementation details. / Diese Diplomarbeit behandelt die Anwendbarkeit der verschiedenen GCC Optimierungsalgorithmen für die TI TMS320C6x Prozessorfamilie. Bedingte und parallele Ausführbarkeit werden zur Beschleunigung eingesetzt. Sie beschreibt den Rahmen in dem die Optimierungen in Version 4.0 des GCC stattfinden und Details zur Implementierung.

At IAV GmbH, Chemnitz, an embedded platform for high-performance sensor data acquisition has been developed. Sensor data is gathered and preprocessed by two digital signal processors (DSP) which communicate bidirectionally via dual-ported memory with the central controlling instance, a Freescale MCF5484 microcontroller running uClinux. The goal of this thesis is to design, implement, analyze and optimize a real-time communication protocol between both DSPs and the microcontroller. The challenges of this thesis can be defined as follows: • A uClinux driver for the dual-ported RAM must be implemented. This driver has to employ the microcontroller’s internal DMA engine and should be integrated into the Linux kernel’s DMA framework. • The DMA engine must be thoroughly analyzed. Especially interesting is its behavior when concurrently performing data transfers. Potential influence factors onto data transfer performance and timing predictability should be experimentally identified and quantitatively characterized, if possible. • Sensor data from the DSPs to the microcontroller has to meet real-time demands and must be prioritized in some way over status and parameter data from and to the DSPs. • Correct and efficient synchronization is a must. If possible, different synchronization schemes should be compared to each other. • The achievable performance in terms of guaranteed and maximum data throughput between DSP and microcontroller as well as end-to-end bandwidth has to be estimated. • Apart from the DMA engine analysis, a general evaluation of potential and achieved performance, timing predictability and the remaining microcontroller’s processing capacity (if any) should be executed.