<p> The thesis is concerned with the design, construction and evaluation of an analog to digital converter based on the "cascade" principle. However, this converter requires only one stage, instead of the usual one stage per bit required by conventional cascade converters. This reduction in the number of stages is achieved by storage in analog form, and by feeding the output of the stage back to its input via a switching network. An 8 bit converter that operates up to a clock frequency of 700KHz was built. The converter is shown to have promising possibilities as a low cost general purpose analog to digital converter. </p> / Thesis / Master of Engineering (MEngr)