The power consumption of Static Random Access Memory (SRAM) has become an important issue for modern integrated circuit design, considering the fact that they occupy large area and consume significant portion of power consumption in modern nanometer chips. SRAM operating in low power supply voltages has become an effective approach in reducing power consumption. Therefore, it is essential to experimentally characterize the single event effects (SEE) of hardened and unhardened SRAM cells to determine their appropriate applications, especially when a low supply voltage is preferred. In this thesis, a SRAM test chip was designed and fabricated with four cell arrays sharing the same peripheral circuits, including two types of unhardened cells (standard 6T and sub-threshold 10T) and two types of hardened cells (Quatro and DICE). The systems for functional and radiation tests were built up with power supply voltages that ranged from near threshold 0.4 V to normal supply 1 V. The test chip was irradiated with alpha particles and heavy ions with various linear energy transfers (LETs) at different core supply voltages, ranging from 1 V to 0.4 V. Experimental results of the alpha test and heavy ion test were consistent with the results of the simulation. The cross sections of 6T and 10T cells present much more significant sensitivities than Quatro and DICE cells for all tested supply voltages and LET. The 10T cell demonstrates a more optimal radiation performance than the 6T cell when LET is small (0.44 MeV·cm2/mg), yet no significant advantage is evident when LET is larger than this. In regards to the Quatro and DICE cells, one does not consistently show superior performance over the other in terms of soft error rates (SERs). Multi-bit upsets (MBUs) occupy a larger portion of total SEUs in DICE cell when relatively larger LET and smaller supply voltage are applied. It explains the loss in radiation tolerance competition with Quatro cell when LET is bigger than 9.1 MeV·cm2/mg and supply voltage is smaller than 0.6 V. In addition, the analysis of test results also demonstrated that the error amount distributions follow a Poisson distribution very well for each type of cell array.

Thesis--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.

Thesis--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 78-89).

A propagação de eventos transientes na lógica combinacional é estudada através da simulação elétrica do circuito, utilizando-se o simulador Hspice. Uma das fontes de falhas transientes é o pulso transiente causado por partículas ionizantes que atingem o circuito. O estudo é centrado nas propriedades de mascaramento elétrico das portas lógicas. Estuda-se a propagação do pulso transiente através de cada estágio da lógica até que alcance um elemento da memória. A partir do estudo das propriedades de mascaramento elétrico, propõe-se um modelo simples para a degradação e ampliação de um pulso transiente enquanto este é propagado através de uma cadeia de portas lógicas. O modelo considera as propriedades elétricas das portas, utilizando como parâmetro principal da modelagem o tempo de propagação (atraso) da porta lógica. O modelo é computacionalmente eficiente e adequado para implementação em ferramentas de auxilio de projeto automatizadas, como ferramentas de timing analysis. A ferramenta timing analysis poderia então executar um algoritmo para percorrer todos os nós de um circuito, determinando os nós mais sensíveis, ajudando a estimar e reduzir a taxa de falhas transientes do circuito. Visando no futuro, testar o modelo e o comportamento de circuitos combinacional sobre efeito de partículas radioativas, foram estudadas algumas arquiteturas existentes capazes de medir a largura dos pulsos transientes nos circuitos combinacionais on-chip, para compararmos com o modelo analítico proposto e os comportamentos elétricos obtidos através de simulação Hspice. / Single Event Transients in Combinatorial Logic are studied using spice-level circuit simulation. The study is centered on the electrical masking properties of the gates. The propagation of the transient through each stage of logic until it reaches a memory element is characterized. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is proposed. The model considers the electrical properties of the logic gates through which the pulse propagates. The model is computationally efficient and intended to be implemented in a timing analysis tool. The timing analysis tool could then implement an algorithm to traverse all circuit nodes, determining the most sensitive nodes, helping to estimate and reduce the soft error failure rate of the whole circuit. Aiming at the future, test the model and the behavior of combinatorial circuits effect on radioactive particles, was studied some existing architectures capable of measuring the width of transient pulses in combinatorial circuits on-chip, to compare with the proposed analytical model and the electrical behaviors obtained by Hspice simulation.

A propagação de eventos transientes na lógica combinacional é estudada através da simulação elétrica do circuito, utilizando-se o simulador Hspice. Uma das fontes de falhas transientes é o pulso transiente causado por partículas ionizantes que atingem o circuito. O estudo é centrado nas propriedades de mascaramento elétrico das portas lógicas. Estuda-se a propagação do pulso transiente através de cada estágio da lógica até que alcance um elemento da memória. A partir do estudo das propriedades de mascaramento elétrico, propõe-se um modelo simples para a degradação e ampliação de um pulso transiente enquanto este é propagado através de uma cadeia de portas lógicas. O modelo considera as propriedades elétricas das portas, utilizando como parâmetro principal da modelagem o tempo de propagação (atraso) da porta lógica. O modelo é computacionalmente eficiente e adequado para implementação em ferramentas de auxilio de projeto automatizadas, como ferramentas de timing analysis. A ferramenta timing analysis poderia então executar um algoritmo para percorrer todos os nós de um circuito, determinando os nós mais sensíveis, ajudando a estimar e reduzir a taxa de falhas transientes do circuito. Visando no futuro, testar o modelo e o comportamento de circuitos combinacional sobre efeito de partículas radioativas, foram estudadas algumas arquiteturas existentes capazes de medir a largura dos pulsos transientes nos circuitos combinacionais on-chip, para compararmos com o modelo analítico proposto e os comportamentos elétricos obtidos através de simulação Hspice. / Single Event Transients in Combinatorial Logic are studied using spice-level circuit simulation. The study is centered on the electrical masking properties of the gates. The propagation of the transient through each stage of logic until it reaches a memory element is characterized. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is proposed. The model considers the electrical properties of the logic gates through which the pulse propagates. The model is computationally efficient and intended to be implemented in a timing analysis tool. The timing analysis tool could then implement an algorithm to traverse all circuit nodes, determining the most sensitive nodes, helping to estimate and reduce the soft error failure rate of the whole circuit. Aiming at the future, test the model and the behavior of combinatorial circuits effect on radioactive particles, was studied some existing architectures capable of measuring the width of transient pulses in combinatorial circuits on-chip, to compare with the proposed analytical model and the electrical behaviors obtained by Hspice simulation.

A propagação de eventos transientes na lógica combinacional é estudada através da simulação elétrica do circuito, utilizando-se o simulador Hspice. Uma das fontes de falhas transientes é o pulso transiente causado por partículas ionizantes que atingem o circuito. O estudo é centrado nas propriedades de mascaramento elétrico das portas lógicas. Estuda-se a propagação do pulso transiente através de cada estágio da lógica até que alcance um elemento da memória. A partir do estudo das propriedades de mascaramento elétrico, propõe-se um modelo simples para a degradação e ampliação de um pulso transiente enquanto este é propagado através de uma cadeia de portas lógicas. O modelo considera as propriedades elétricas das portas, utilizando como parâmetro principal da modelagem o tempo de propagação (atraso) da porta lógica. O modelo é computacionalmente eficiente e adequado para implementação em ferramentas de auxilio de projeto automatizadas, como ferramentas de timing analysis. A ferramenta timing analysis poderia então executar um algoritmo para percorrer todos os nós de um circuito, determinando os nós mais sensíveis, ajudando a estimar e reduzir a taxa de falhas transientes do circuito. Visando no futuro, testar o modelo e o comportamento de circuitos combinacional sobre efeito de partículas radioativas, foram estudadas algumas arquiteturas existentes capazes de medir a largura dos pulsos transientes nos circuitos combinacionais on-chip, para compararmos com o modelo analítico proposto e os comportamentos elétricos obtidos através de simulação Hspice. / Single Event Transients in Combinatorial Logic are studied using spice-level circuit simulation. The study is centered on the electrical masking properties of the gates. The propagation of the transient through each stage of logic until it reaches a memory element is characterized. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is proposed. The model considers the electrical properties of the logic gates through which the pulse propagates. The model is computationally efficient and intended to be implemented in a timing analysis tool. The timing analysis tool could then implement an algorithm to traverse all circuit nodes, determining the most sensitive nodes, helping to estimate and reduce the soft error failure rate of the whole circuit. Aiming at the future, test the model and the behavior of combinatorial circuits effect on radioactive particles, was studied some existing architectures capable of measuring the width of transient pulses in combinatorial circuits on-chip, to compare with the proposed analytical model and the electrical behaviors obtained by Hspice simulation.

The memory cells used in modern field programmable gate arrays (FPGAs) are highly susceptible to single event upsets (SEUs). The typical mitigation strategy in the industry is some form of hardware redundancy in the form of duplication with comparison (DWC) or triple modular redundancy (TMR). While this strategy is highly effective in masking out the effect of faults, it incurs a large hardware cost. In this thesis, we explore a different approach to hardware redundancy. The core idea of our approach is to exploit the conflict-driven clause learning (CDCL) mechanism in modern Boolean satisfiability (SAT) solvers to provide us with invariants which can be realized as hardware checkers. Furthermore, we develop the algorithms required to select a subset of these invariants to be included as part of a checker circuit. This checker circuit then augments the original FPGA design. We find which look-up table (LUT) memory cells are sensitive to bitflips, then we automatically generate a checker circuit consisting of hardware invariants targeted towards those faults. We aim to reach 100% coverage of sensitizable faults. After extensive experimentation, we conclude that this approach is not competitive with DWC with respect to hardware area. However, we demonstrate that many bitflips will have reduced a detection latency compared to DWC. / Thesis / Master of Applied Science (MASc)

Efeitos causados pela interação da radiação ionizante em dispositivos eletrônicos consis- tem numa preocupação crescente em diversos segmentos, como as aplicações aeroespaci- ais e em física de altas energias. Entre os efeitos de radiação induzidos por íons pesados estão os chamados de Efeitos de Eventos Isolados (Single Event Effects - SEE), em que o impacto de um único íon pode ser capaz de gerar um efeito observável, através da elevada deposição de energia e consequente geração de pares elétron-lacuna. O estudo destes efeitos requer um acelerador de partículas capaz de prover feixes uniformes de íons pesados com baixo fluxo. Neste trabalho, desenvolvemos um sistema para produ- ção de feixes de íons pesados para estudar SEE no Acelerador Pelletron 8UD, utilizando as técnicas de desfocalização e espalhamento múltiplo em folhas de ouro. O sistema foi projetado para prover feixes com intensidades entre 10 2 e 10 5 partículas/s/cm 2 com uniformidade maior que 90% numa área circular de diâmetro de 1,5 cm, operando em regime de alto-vácuo. Um manipulador de amostras permite a movimentação do dispo- sitivo sob teste com precisão de 2,5 m e um sistema de aquisição de dados dedicado foi desenvolvido, permitindo a automação de medidas. O sistema foi caracterizado com feixes de 1 H, 12 C, 16 O, 19 F, 28 Si, 35 Cl e 63 Cu a várias energias, apresentando fluxo e uni- formidade adequados aos experimentos em diversas configurações de focalização e folhas espalhadoras, e tem sido utilizado por diversos grupos de pesquisa. O novo sistema foi utilizado para estudar o efeito das camadas de isolamento e metalização na coleta de carga e geração de eventos observáveis em um dispositivo analógico e em um disposi- tivo digital, de modo a estabelecer metodologias de trabalho adequadas para estudos precisos de mecanismos de ocorrência de efeitos de radiação. O dispositivo analógico estudado foi um transistor p-MOS, onde o sinal de corrente induzido pelo impacto de íons diversos foi analisado de modo a obter a seção de choque de eventos e a cargaix gerada, permitindo determinar a espessura da camada de metalização em 1,28(2) m, e a camada de coleta de carga dependente do LET e alcance da partícula incidente, variando entre 6,0 e 11,0 m. O dispositivo digital estudado foi uma memória SRAM 28nm, onde foi observada uma forte dependência da seção de choque de eventos com a penetração do feixe no dispositivo. Associando as camadas de metalização e isolamento a um meio efetivo de interação, obteve-se que toda a área sensível do dispositivo só pode ser excitada, isto é, nela ocorrerem eventos observáveis, para partículas com alcance, no meio efetivo, entre 14 e 20 m, embora partículas com alcance de até 10 m sejam capazes de sensibilizar até 50% da área ativa do dispositivo. / Effects on electronic devices caused by interactions of ionizing radiation are a main concern in several fields, such as aerospace applications and high-energy physics. Among the heavy-ion induced radiation effects are the Single Event Effects, in which a strike of a single ion can be enough to generate an observable effect, as a result of the high energy deposition and thus electron-hole pairs generation. The study of these effects requires the use of uniform, low-flux particle beams. In this work, we developed a system for production of heavy ion beams for SEE studies at Pelletron 8UD accelerator, through the defocusing and multiple scattering in gold foil techniques. The setup can provide ion beams with intensities ranging from 10 2 e 10 5 particles/s/cm 2 with uniformity better than 90% in an circular area of 1.5 cm diameter, operating under high-vacuum. A sample manipulador allows device under test positioning with a precision of 2.5 m, and a dedicated data acquisition system was developed, allowing measurement automation. The system was characterized with 1 H, 12 C, 16 O, 19 F, 28 Si, 35 Cl and 63 Cu ion beams at several energies, presenting flux and uniformity adequate for SEE studies in many different configurations, and it is being used by several research groups. The new facility was used to study the effect of isolation and metalization layers in charge collection and observable events generation in an analog and in a digital device, in order to establish proper metodologies for precise studies of radiation effects mecanisms. The analog device studied was a p-MOS transitor, from which the heavy-ion impact induced current signal was analised to obtain cross-section and colected charge, allowing to determine metalization layer thickness to be 1.28(2) m, and charge collection dependency on particle LET and range, varying from 6.0 to 11.0 m. The digital device studied was a 28nm SRAM memory, where a strong dependency of cross-section with particle range in the device was observed. Associating to the metal and insulating layers an effectivexi medium, it was observed that the complete sensitive area can be excited only by particle with ranges in effective medium between 14 and 20 m, although particles with ranges up to 10 m are capable of sensibilizing up to 50% of devices active area.

The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. Among these noise sources, soft errors (or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as combinational logic circuits. Also, in the DSM era, process variations are increasing at an alarming rate, making it more difficult to design reliable VLSI circuits. Hence, it is important to efficiently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this dissertation presents several analysis and design techniques with the goal of realizing VLSI circuits which are tolerant to radiation particle strikes and process variations. This dissertation consists of two parts. The first part proposes four analysis and two design approaches to address radiation particle strikes. The analysis techniques for the radiation particle strikes include: an approach to analytically determine the pulse width and the pulse shape of a radiation induced voltage glitch in combinational circuits, a technique to model the dynamic stability of SRAMs, and a 3D device-level analysis of the radiation tolerance of voltage scaled circuits. Experimental results demonstrate that the proposed techniques for analyzing radiation particle strikes in combinational circuits and SRAMs are fast and accurate compared to SPICE. Therefore, these analysis approaches can be easily integrated in a VLSI design flow to analyze the radiation tolerance of such circuits, and harden them early in the design flow. From 3D device-level analysis of the radiation tolerance of voltage scaled circuits, several non-intuitive observations are made and correspondingly, a set of guidelines are proposed, which are important to consider to realize radiation hardened circuits. Two circuit level hardening approaches are also presented to harden combinational circuits against a radiation particle strike. These hardening approaches significantly improve the tolerance of combinational circuits against low and very high energy radiation particle strikes respectively, with modest area and delay overheads. The second part of this dissertation addresses process variations. A technique is developed to perform sensitizable statistical timing analysis of a circuit, and thereby improve the accuracy of timing analysis under process variations. Experimental results demonstrate that this technique is able to significantly reduce the pessimism due to two sources of inaccuracy which plague current statistical static timing analysis (SSTA) tools. Two design approaches are also proposed to improve the process variation tolerance of combinational circuits and voltage level shifters (which are used in circuits with multiple interacting power supply domains), respectively. The variation tolerant design approach for combinational circuits significantly improves the resilience of these circuits to random process variations, with a reduction in the worst case delay and low area penalty. The proposed voltage level shifter is faster, requires lower dynamic power and area, has lower leakage currents, and is more tolerant to process variations, compared to the best known previous approach. In summary, this dissertation presents several analysis and design techniques which significantly augment the existing work in the area of resilient VLSI circuit design.

abstract: An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing. Spatial separation of critical nodes in the physical design of this approach mitigates multi-node charge collection (MNCC) upsets. An advanced encryption system implemented with the proposed design, compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation up to 18% over an improved version of the prior approach, with negligible area impact. It can save up to 2/3rd of the power consumption and reach maximum possible frequency, when used in non-redundant mode of operation. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2015