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This master thesis examines the design, manufacturing and characterization of a miniaturized ceramic pressure gauge to be integrated into a system for carbon isotope analysis. Carbon isotope analysis can be used to find traces of extraterrestrial life. Screen printing, platinum bond wire threading, milling, lamination and sintering processes have been developed in order to manufacture a robust, temperature stable and chemically inert component potentially integratable to the carbon isotope analysis system. With use of the Pirani principle, which measures the pressure dependent thermal conductivity of air, promising results have been observed. A relative resistance change of 6 % within the pressure range of 1-10 Torr has been observed. This is comparable to, and even greater than, previous studies. The device has a good response for the desired pressure range. The device sensitivity was studied with different currents and geometric parameters. The results showed that the sensitivity is highly dependent on current and air volume. The work has been done at the Ångström Space Technology Centre –­­ a research group within the Ångström Laboratory, Uppsala University – which currently researches on microscale systems for, e.g., space exploration.

The National Aeronautics and Space Administration maintains a challenging schedule of planned and on-going space exploration missions that extend to the outer reaches of our galaxy. New missions represent a huge investment, in terms of actual costs for equipment and support infrastructure, and personnel training. The success of a mission is critical considering both the monetary investment, and for manned missions, the lives which are put at risk. Tragedies involving Challenger, Columbia, Apollo 7, and the near tragedy of Apollo 13 exemplify that space exploration is a dangerous endeavor, posing extreme environmental conditions on both equipment and personnel. NASA, the National Science Foundation' and numerous independent researchers indicate that predictive simulations have the potential to decrease risk and increase efficiency and effectiveness in space exploration activity. Simulations provide the capability to conduct planning and rehearsal of missions, allowing risk reducing designs and techniques to be discovered and tested. Real-time simulations may improve the quality of the response in a real-time crisis situation. The US Army developed Layered Terrain Format (LTF) database is a uniquely architected database approach that provides high fidelity representation of terrain and specialized terrain query functions that are optimized to support real-time simulations. This dissertation investigates the question; can the unique LTF database architecture be applied to the general problem of celestial body representation? And if so, what benefits might it bring for mission planners and personnel executing the mission? Due to data limitations, this research investigates these questions through a lunar analog setting iv involving S band and Earth-bound communication signals as might be needed to conduct manned and/or robotic mission on the moon. The target terrain data set includes portions of the Black Point Lava Flow in Arizona which will be used for NASA's 2010 Desert RATS analog studies. Applied Research Associates Inc, the developer of the LTF product, generated Black Point databases and made limited modifications to the LTF Viewer tool, RAVEN, which is used for visualization of the database. Through the results attained during this research it is concluded that LTF product does provide a useful simulation capability which could be used by mission personnel both in pre-mission planning and during mission execution. Additionally, LTF is shown to have application an information system, allowing geospecific data of interest to the mission to be implemented within its layers. The Florida Space Research & Education Grant Program sponsored by FSGC, Space Florida and UCF provided a grant of $31,500 to perform this research.

The automatic generation of instruction set extensions to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. There have been incremental improvements in the quality of the algorithms that discover and select which instructions to add to a processor. The use of automatic algorithms, however, result in instructions which are radically different from those found in conventional, human-designed, RISC or CISC ISAs. This has resulted in a gap between the hardware’s capabilities and the compiler’s ability to exploit them. This thesis proposes and investigates the use of a high-level compiler pass that uses graph-subgraph isomorphism checking to exploit these complex instructions. Operating in a separate pass permits techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. The existing, mature, compiler back-end can then handle the remainder of the compilation. With this method, the high-level pass was able to use 1965 different automatically produced instructions to obtain an initial average speed-up of 1.11x over 179 benchmarks evaluated on a hardware-verified cycle-accurate simulator. This result was improved following an investigation of how the produced instructions were being used by the compiler. It was established that the models the automatic tools were using to develop instructions did not take account of how well the compiler could realistically use them. Adding additional parameters to the search heuristic to account for compiler issues increased the speed-up from 1.11x to 1.24x. An alternative approach using a re-designed hardware interface was also investigated and this achieved a speed-up of 1.26x while reducing hardware and compiler complexity. A complementary, high-level, method of exploiting dual memory banks was created to increase memory bandwidth to accommodate the increased data-processing bandwidth provided by extension instructions. Finally, the compiler was considered for use in a non-conventional role where rather than generating code it is used to apply source-level transformations prior to the generation of extension instructions and thus affect the shape of the instructions that are generated.

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Spur-of-the-moment planetary exploration missions are within our reach. Complex systems and complex missions usually take years of planning and force launches to become incredibly expensive. We argue here for cheap, fast missions using large numbers of mass produced simple autonomous robots that are small by today's standards, perhaps 1 to 2kg. We suggest that within a few years it will be possible, at modest cost, to invade a planet with millions of tiny robots.

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Advanced Encryption Standard is new standard for data encryption and decryption.There is a lot of relevant research so far, but how to find out the suitable design according to the demand has become an important question. So we consult different improvement methods from relevant research, do the design space exploration of AES hardware circuit design with the modeling of parameterized IP Generator.We choose non-feedback mode AES design, which can offer higher security. Using the submodule as different design parameter such as SubBytes/InvSubBytes¡BMixColumns/InvMixColumns¡BKeyExpansion to form many kinds of AES hardware circuit. SubBytes/InvSubBytes¡BMixColumns/InvMixColumns module include two different structure, Integrated and Separate Encryption/Decryption module. KeyExpansion module include two different structure, on the fly and Store in Rom.There are three different keylength 128¡B192¡B256, which can form forteen different structure. We provide circuit gate count¡Bthroughput¡Bpower consumption information of different AES hardware citcuit design by the synthesis and gate-level simulation result. According to our implementation, the user can choose the suitable AES hardware circuit design method and which can solve the problem above. We also provide an automatic test pattern generator for our design verification, it makes our design can be integrated efficiently. Our experiment result show that, the design which Encryption/Decryption module use integrated structure have less circuit gate count than which Encryption/Decryption module use separate structure while throughput constraint is between 700MHz to 1300MHz (It¡¦s depend on different keylength combination). But while the throughput constraint become higher, the circuit gate count of integrated structure rise faster than separate structure. And the situation is the same with power consumption.The maximum throughput of KeyExpansion module use store in Rom structure is higher than whcich use on the fly structure.

Design Space Exploration is the task of identifying optimal implementation architectures for an application. On the front-end, it involves multi-objective optimization through a large space of options, and lends itself to a multitude of algorithmic approaches. On the back-end, it relies extensively on common capabilities such as model refinement, simulation and assessment of parameters like performance and cost. These characteristics present an opportunity to create an infrastructure that enables multiple approaches to be deployed using generic back-end services. In this work, we describe such a framework, developed using the System-on-Chip Environment, and we demonstrate the benefits and feasibility of deploying a variety of design space exploration approaches built on top of this basic infrastructure. / text

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