This thesis describes design techniques for high-performance switched-capacitor (SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of component imperfections, such as nonlinear op-amp voltage transfer characteristics, capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise. Various correlated-double-sampling (CDS) schemes are discussed, and some novel predictive CDS schemes are proposed. Analysis, simulation and experimental results show that these schemes are very effective for reducing the effects of op-amp imperfections, resulting in lower signal distortion and reduced low-frequency noise and dc offset. The effect of capacitor nonlinearity in an SC circuits is analyzed in detail, and techniques for linearization are discussed. Applying these techniques, MOSFET capacitors can be used in high-performance digital-process-compatible SC circuit designs. To verify the effectiveness of the proposed techniques, three prototype chips containing a 3-V all-MOSFET delta-sigma modulator, predictive gain- and offset-compensated track-and-hold stages, and SC amplifiers with various CDS techniques, were designed and fabricated in 1.2 ��m CMOS technology. The measured results show that these circuit techniques are highly effective in high-performance SC circuit designs. / Graduation date: 1997

Voltage converters or charge pumps find their use in many circuits. They are extensively used in hand held devices as cell phones, pagers, PDA's and laptops. Some of the important issues relating to design of voltage regulators for handheld devices are size, efficiency and noise. Another important factor to be considered is the discharge characteristic of the various batteries used by the handheld devices. This thesis addresses the issues of tones present in the conventional switched capacitor voltage regulator. An alternate architecture with a delta-sigma control loop to eliminate this problem is proposed. Also discussed is a method to compute the efficiency of switched capacitor charge pumps. A test chip implementing the new architecture was fabricated in a 0.72-micron CMOS process. The results of the test chip verify the improved architecture. / Graduation date: 2002

It has been verified by theoretical analysis, circuit simulation and test that two switch transistors in parallel in a simple sample and hold circuit can be achieve high speed with low error voltage due to charge injection. The wide transistor provides low RC time constant when it is closed and the narrow one ensures a low error voltage. However, tradeoff can be made in a specific application. A concise analytical expression for switch-induced error voltage on a switched capacitor is derived in this thesis. It can help designer to make the optimum decision. Experimentally, it was found that the optimum size of the wide transistor is several times wider than the narrow one. Delayed clock scheme can be used to make charge injection signal-independent in a basic integrator structure. Using two transistors with different sizes and clock duty cycles in parallel can take advantage of the fast speed of the wide transistor and the small charge injection error of the small transistor. However, the combination of the two devices, including the size and clock duty cycles, should be chosen carefully to achieve the improvement. / Graduation date: 1998

In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction of distortion, two capacitors can be connected in series or in parallel so that a first-order cancellation of the nonlinearity can be achieved. Experimental results demonstrated that the among these techniques series compensation is the most effective for reducing the nonlinearity of MOSFET capacitors. A novel predictive SC amplifier has been proposed for its insensitivity to op-amp imperfections. Experimental results show that the S/THD of the predictive SC amplifier was 10 dB larger than that of the non-predictive one. It was also shown that a predictive circuit was effective for reducing the nonlinearity caused by the op-amp and/or the MOSFET capacitors. It has been demonstrated that a two-stage op-amp with a large output swing can be fabricated in a standard digital CMOS process. The frequency compensation was accomplished using a source follower and a MOSFET capacitor. An SC amplifier using this two-stage op-amp and double-poly capacitors was fabricated, and it exhibited a large linear output range. A MOSFET-only digitally controlled gain/loss circuit was designed and fabricated in a 1.2�� CMOS process. It demonstrated that the series compensation is effective not only for a large output swing in an amplifier, but also for a large input swing in an attenuator. A pipeline D/A converter utilizing MOSFET capacitors was designed as another application of charge processing technique. It consisted of three parts: a V-Q conversion stage, a charge transfer stage, and a Q-V converter. A new switch configuration which enables the series compensation to have a large bias voltage has also been proposed. It was shown that it works well, and it will be helpful for low-voltage operation, too. / Graduation date: 1998

Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass delta-sigma modulator architectures exchange higher clock rates with hardware complexity. For a given oversampling ratio (OSR), the multiplexed first-order delta-sigma modulator achieves a higher resolution. Guaranteed stability is a very desirable feature of these structures. The multi-loop delta-sigma modulator architecture similarly reduces the number of integrators needed to achieve high-resolution conversion for a given OSR. To ensure stability a quantizer with (N+1) bits must be used, where N is the number of loops, or in other words, the order of the delta-sigma modulator. Digital correction or randomizing techniques can be used to eliminate the performance reduction due to digital-to-analog- (D/A) converter nonlinearity error [59], [64]. Bandpass delta-sigma modulators are useful for applications such as AM radio receivers, spectrum analyzers, and digital wireless systems. Using z --> -z[superscript N] or z --> z[superscript N] mapping, a low pass delta-sigma modulator can be transformed to a bandpass one. One of the methods to implement the loop filters in bandpass delta-sigma modulators is to use Pseudo-N-Path (PNP) switched-capacitor (SC) integrators. The advantage is that the center frequency occurs exactly at an integer division of the sampling frequency because of the number of physical paths. To achieve maximum resolution, integrators that do not suffer from clock feedthrough peaks are needed. The proposed differential and single-ended novel PNP integrators address this problem [76]. To keep the opamp specifications less stringent while achieving high resolution, these PNP integrators have been further improved with gain compensation techniques [53]. / Graduation date: 1997

Graduation date: 1994

Graduation date: 1991

Includes bibliographical references (p. 118-120).

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 62-64). Also available in electronic version. Access restricted to campus users.

Thesis (M. Eng.)--Carleton University, 1988. / Also available in electronic format on the Internet.