International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / The success of the client/server paradigm for modern networked telemetry systems continues to stress the LAN that carries data generated from the acquisition front ends to the display workstations and the file servers on the LAN. As the number of LAN-attached devices such as Loral's System 500 Model 550 (Loral 550) telemetry front end, workstations, and file servers grows beyond two, the Ethernet LAN collision rates increase and the throughput slows down. At what point the network performance declines is a function of the specific application bandwidth demands required. This paper describes a new method for boosting LAN performance by providing Ethernet switching and protocol filtering. The performance of the LAN is critical to the performance of the complete telemetry enterprise architecture.

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In this work a new voltage buffer, the drain-follower, achieves 300MHz band-width with 2pF load, a dc gain of 0.993V/V, 1mV offset voltage, -60 dB total harmonic distortion at 1.4Vpp output voltage and 6.5mW power dissipation from 5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented in 0.5��m CMOS technology. The circuit has been sent for fabrication. Simulation results of the biquad filter indicate operation at 100MHz with 20mW power consumption from a 5V supply can be achieved. / Graduation date: 2002

This thesis describes design techniques for high-performance switched-capacitor (SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of component imperfections, such as nonlinear op-amp voltage transfer characteristics, capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise. Various correlated-double-sampling (CDS) schemes are discussed, and some novel predictive CDS schemes are proposed. Analysis, simulation and experimental results show that these schemes are very effective for reducing the effects of op-amp imperfections, resulting in lower signal distortion and reduced low-frequency noise and dc offset. The effect of capacitor nonlinearity in an SC circuits is analyzed in detail, and techniques for linearization are discussed. Applying these techniques, MOSFET capacitors can be used in high-performance digital-process-compatible SC circuit designs. To verify the effectiveness of the proposed techniques, three prototype chips containing a 3-V all-MOSFET delta-sigma modulator, predictive gain- and offset-compensated track-and-hold stages, and SC amplifiers with various CDS techniques, were designed and fabricated in 1.2 ��m CMOS technology. The measured results show that these circuit techniques are highly effective in high-performance SC circuit designs. / Graduation date: 1997

Two novel clock feedthrough compensation circuits for switched - current (SI) memory cells are proposed to reduce the clock feedthrough error. One is a current compensation first generation SI memory cell and another is an error voltage reduction second generation SI memory cell. Both circuits are designed using a 0.5£gm UMC CMOS process. In this study, the first circuit has obtained an accuracy about 0.1% error with a frequency of 5MHz, and the second circuit has achieved 0.12% error in accuracy with 10.5MHz in frequency. The results are obtained by SPICE simulates.

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Voltage converters or charge pumps find their use in many circuits. They are extensively used in hand held devices as cell phones, pagers, PDA's and laptops. Some of the important issues relating to design of voltage regulators for handheld devices are size, efficiency and noise. Another important factor to be considered is the discharge characteristic of the various batteries used by the handheld devices. This thesis addresses the issues of tones present in the conventional switched capacitor voltage regulator. An alternate architecture with a delta-sigma control loop to eliminate this problem is proposed. Also discussed is a method to compute the efficiency of switched capacitor charge pumps. A test chip implementing the new architecture was fabricated in a 0.72-micron CMOS process. The results of the test chip verify the improved architecture. / Graduation date: 2002

It has been verified by theoretical analysis, circuit simulation and test that two switch transistors in parallel in a simple sample and hold circuit can be achieve high speed with low error voltage due to charge injection. The wide transistor provides low RC time constant when it is closed and the narrow one ensures a low error voltage. However, tradeoff can be made in a specific application. A concise analytical expression for switch-induced error voltage on a switched capacitor is derived in this thesis. It can help designer to make the optimum decision. Experimentally, it was found that the optimum size of the wide transistor is several times wider than the narrow one. Delayed clock scheme can be used to make charge injection signal-independent in a basic integrator structure. Using two transistors with different sizes and clock duty cycles in parallel can take advantage of the fast speed of the wide transistor and the small charge injection error of the small transistor. However, the combination of the two devices, including the size and clock duty cycles, should be chosen carefully to achieve the improvement. / Graduation date: 1998