Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 80-81). Also available on the World Wide Web.

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This thesis deals with the time-domain analysis of switched linear networks and investigates inherent problems which have to be considered when analyzing this class of networks. Computer simulation requires the use of numerical methods and we focus on the transmission -line modelling technique (TLM) and the numerical inverse Laplace transform. A general approach based on the one-graph modified nodal description is given which allows the formulation of circuit equations of a TLM-modelled circuit by inspection. The numerical equivalence of TLM and trapezoidal rule has been found and a proof is given. A variable step size simulator has been developed based on the 4th order numerical inverse Laplace transform. The properties of this method are reviewed and its limitations are discussed. Simulation results are given to illustrate capabilities of the simulator.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

by Wai-Shan Chan. / Thesis submitted in: August 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 61-63). / Chapter Chapter 1 --- Introduction / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Fiber recirculating delay loop --- p.2 / Chapter 1.3 --- Slicing scheme --- p.3 / Chapter 1.4 --- Outline of the thesis --- p.4 / Chapter Chapter 2 --- Fiber recirculating delay loop / Chapter 2.1 --- Review --- p.5 / Chapter 2.1.1 --- Introduction --- p.5 / Chapter 2.1.2 --- The device --- p.6 / Chapter 2.1.3 --- Filtering properties of the fiber recirculating delay loop --- p.8 / Chapter 2.1.4 --- Noise properties of the fiber recirculating delay loop --- p.10 / Chapter 2.1.5 --- Limitations of the BRL device --- p.13 / Chapter 2.2 --- Discussion --- p.14 / Chapter 2.3 --- Summary --- p.14 / Chapter Chapter 3 --- Slicing scheme / Chapter 3.1 --- Introduction --- p.16 / Chapter 3.2 --- Slicing Scheme --- p.18 / Chapter 3.3 --- Experimental Investigation --- p.20 / Chapter 3.4 --- Numerical analysis --- p.33 / Chapter 3.5 --- Simulations --- p.40 / Chapter 3.6 --- Discussion --- p.49 / Chapter 3.6.1 --- The relationship between the system penalty and the ratio fd/fs --- p.49 / Chapter 3.6.2 --- Design of BRL --- p.51 / Chapter 3.6.3 --- Advantages and Disadvantages of the slicing scheme --- p.56 / Chapter 3.7 --- Summary --- p.56 / Chapter Chapter 4 --- Conclusion / Chapter 4.1 --- Fiber recirculating delay loop as a BRL device --- p.58 / Chapter 4.2 --- Slicing scheme --- p.59 / Chapter 4.3 --- Future work --- p.60 / Bibliography --- p.61

Graduation date: 2004

Clock-feedthrough effects, channel-length modulation and device mismatch are the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these non-ideal effects are analyzed. A high-performance current mirror, namely regulated cascode current mirror, which eliminates drain voltage variation problem is introduced. By using this current mirror as a basic memory cell, a clock-feedthrough cancellation circuit is developed, which ideally solves the clock-feedthrough and drain voltage variation problems. A fifth-order SI lowpass Chebyshev ladder filter is built using the proposed cancellation circuit and implemented in a two-micron P-well standard digital CMOS process by MOSIS. Another emerging technique, dynamic current mirrors or current copiers, is introduced. Improved dynamic current mirror cell and dynamic current mirror-based integrators have been developed. / Graduation date: 1992

Title from PDF of title page (University of Missouri--Columbia, viewed on March 10, 2010). The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Thesis advisor: Dr. Robert M O'Connell. Includes bibliographical references.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Mary Ann Ingram, Committee Member; Lim, Sung Kyu, Committee Member; Riley, George F., Committee Member; Mooney III, Vincent J., Committee Chair; Pande Santosh, Committee Member. Includes bibliography.

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