The power density of a switching converter is dependent on the size of the power circuit components. Converters are operated in the hundreds of kHz to achieve high power density since the size of the converter reactive components decrease as frequency increases. Most present day low power (<200W) DC-DC converters operate at switching frequencies up to 500kHz. Some research has been conducted on converters that can operate above 500kHz up to 4MHz. In the near future, most DC-DC switching converters for communications and computers will operate at switching frequencies of 1-10MHz in order to achieve greater power density and improved transient response. To meet the next generation requirements of these applications, four new ideas are proposed in this thesis. The first contribution is a new current source gate drive circuit for power MOSFETs. The circuit provides a nearly constant gate current to reduce switching transition times and therefore switching loss in power MOSFETs. In addition, it can recover a portion of the gate energy normally dissipated in a conventional driver. Demonstrated loss reduction of 24.8% at 10V/5A load are presented in comparison to a conventional voltage source driver for a boost converter switching at 1MHz. The second contribution is a new high efficiency 1MHz synchronous buck voltage regulator using an improved current source driver. The proposed circuit achieves short rise and fall times to reduce switching loss in the buck HS MOSFET. It also recovers a portion of the SR gate energy, enabling a loss reduction of 24% at 1.3V/30A load in comparison to a conventional driver. In the third contribution, a new switching loss model is proposed for synchronous buck voltage regulators. The model uses simple closed form equations to calculate the rise and fall times and piecewise linear approximations of the HS MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss. The final contribution is a new variable frequency digital control method for resonant converters, which is suitable for future applications switching at 10MHz. The proposed method uses frequency dithering to reduce the clock frequency demands of the digital controller. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-02-28 10:56:06.732