The power density of a switching converter is dependent on the size of the power circuit components. Converters are operated in the hundreds of kHz to achieve high power density since the size of the converter reactive components decrease as frequency increases. Most present day low power (<200W) DC-DC converters operate at switching frequencies up to 500kHz. Some research has been conducted on converters that can operate above 500kHz up to 4MHz. In the near future, most DC-DC switching converters for communications and computers will operate at switching frequencies of 1-10MHz in order to achieve greater power density and improved transient response. To meet the next generation requirements of these applications, four new ideas are proposed in this thesis. The first contribution is a new current source gate drive circuit for power MOSFETs. The circuit provides a nearly constant gate current to reduce switching transition times and therefore switching loss in power MOSFETs. In addition, it can recover a portion of the gate energy normally dissipated in a conventional driver. Demonstrated loss reduction of 24.8% at 10V/5A load are presented in comparison to a conventional voltage source driver for a boost converter switching at 1MHz. The second contribution is a new high efficiency 1MHz synchronous buck voltage regulator using an improved current source driver. The proposed circuit achieves short rise and fall times to reduce switching loss in the buck HS MOSFET. It also recovers a portion of the SR gate energy, enabling a loss reduction of 24% at 1.3V/30A load in comparison to a conventional driver. In the third contribution, a new switching loss model is proposed for synchronous buck voltage regulators. The model uses simple closed form equations to calculate the rise and fall times and piecewise linear approximations of the HS MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss. The final contribution is a new variable frequency digital control method for resonant converters, which is suitable for future applications switching at 10MHz. The proposed method uses frequency dithering to reduce the clock frequency demands of the digital controller. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-02-28 10:56:06.732

Insulated Gate Bipolar Transistor (IGBT) based voltage source converter (VSC) applica-tions embedded in power systems are growing. Optimal design of thermal management systems for such converters requires estimation of IGBT losses under various operating conditions, both normal and abnormal. Therefore, development of tools for estimating IGBT losses in EMT simulators is important as converters embedded in large power sys-tems are simulated in EMT simulators. Two circuit models are developed to simulate turn-on and turn-off transients using a be-havioral approach. These circuit models mimic the observed behavior in distinct phases of the turn-on and turn-off transients under the inductive load switching. In this model, the nonlinear nature of the circuit model of the IGBT is treated and converter specific in-fluential parameters are taken in to account. An excellent correlation between the meas-ured and simulated waveforms as well as measured and estimated switching losses is ob-served. Finally, an efficient method to incorporate switching loss calculation in an EMT program in the form of a lookup table created using the developed transient model is pro-posed.

Insulated Gate Bipolar Transistor (IGBT) based voltage source converter (VSC) applica-tions embedded in power systems are growing. Optimal design of thermal management systems for such converters requires estimation of IGBT losses under various operating conditions, both normal and abnormal. Therefore, development of tools for estimating IGBT losses in EMT simulators is important as converters embedded in large power sys-tems are simulated in EMT simulators. Two circuit models are developed to simulate turn-on and turn-off transients using a be-havioral approach. These circuit models mimic the observed behavior in distinct phases of the turn-on and turn-off transients under the inductive load switching. In this model, the nonlinear nature of the circuit model of the IGBT is treated and converter specific in-fluential parameters are taken in to account. An excellent correlation between the meas-ured and simulated waveforms as well as measured and estimated switching losses is ob-served. Finally, an efficient method to incorporate switching loss calculation in an EMT program in the form of a lookup table created using the developed transient model is pro-posed.

The ultimate goal for power electronics is to convert one form of raw electrical energy into a usable power source with the lowest amount of loss. A considerable portion of these losses are due to the use of switching devices themselves. Device losses can be apportioned to conduction loss and switching loss. It is commonly known and practiced that conduction loss can be reduced by driving MOSFETs and IGBTs harder with gate voltages closer to the maximum rating. This lowers the voltage across the device in the path of the amplified current and ultimately reduces power dissipated by the device. However, switching losses of these devices are not as easily characterized or intuitive for power electronics designers. This is mainly due to the fact that the parasitic reactive elements are nonlinear and not as readily documented as I-V characteristics of a given power device. For example, non-linear parasitic capacitances in the device are given for a fixed frequency across a voltage sweep. Parasitic inductance is typically not even mentioned in the datasheet. The switching losses of these devices depend on these mysterious reactances. A functional way to obtain estimates of switching loss is to test the device under the conditions the device will be used. However, this task must be approached carefully in order to accurately measure the voltage and current of the device. Measurement devices also have parasitic impedances of their own that can add or subtract to switching energy during turn on or turn off and create misleading results. Preliminary testing was performed on multiple devices. After preliminary testing and deliberation, a device-measurement printed circuit board was made to easily replace switching devices of the same package. This thesis presents switching loss measurements of medium-power capable devices in the tens of kW range. It also aims to attribute characteristics of switching voltage and current waveforms to the internal structure of the devices. The device tester designed is versatile since the output buffer of the gate drive is comprised of D-PAK totem pole BJTs. This is able to drive both current and voltage driven devices, i.e. SiC J-FETs (current-driven) and other voltage-driven devices (i.e. MOSFETs and IGBTs). It also allows for TO-220 and TO-247 packaged power diodes. / Master of Science

ABSTRACT Digitally-Controlled Two-Phase Zero-Voltage-Switching Quasi-Resonant Buck Converter Brian Luc This thesis entails the design, construction, and performance analysis of a digitally-controlled two-phase Zero-Voltage Switching Quasi-Resonant (ZVS-QR) buck converter. The converter is aimed to address the issues associated with powering CPUs operating at lower voltage and high current. To evaluate its performance, the Two-Phase ZVS-QR buck converter is compared against a traditional Two-Phase buck converter. The design procedure required to implement both converters through utilizing the characterization curve and formulas derived from their circuit configurations will be presented. Computer simulation of the Two-Phase ZVS-QR buck converter is provided to exhibit its operation and potential for use in low voltage and high current applications. In addition, hardware prototypes for both ZVS-QR and traditional buck converters are constructed utilizing a Programmable Interface Controller (PIC). Results from hardware tests demonstrate the success of using digital controller for the 60W 12VDC to 1.5VDC ZVS-QR buck converter. Merits and drawbacks based on the operation and performance of both converters will also be assessed and described. Further work to improve the performance of ZVS-QR will also be presented. Keywords: Buck Converter; Zero-Voltage-Switching; Multi-Phase; Efficiency; Switching Loss

Indiana University-Purdue University Indianapolis (IUPUI) / There are various types of power electronic converters available in recent days. In some applications (e.g. PC power supply), it is required to supply more than one load from a single power supply. One of the main challenges while designing a power converter is to increase its e ciency especially when the number of power switches employed is relatively large. While several loads are supplied from a single source, if the power loss in the switches cannot be reduced, then the expected utilization of using a single source is not very feasible. To reduce the loss and increase e ciency, the thesis presents a novel design with reduced number of switches. The scope of this thesis is not limited to the dc-dc converter only, the converter to supply three phase ac loads from a single dc source is also presented. This discussion includes an improved fault tolerant configuration of the inverter part. The generated waveforms from the simulations are included as a demonstration of satisfactory results.

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The high penetration of renewable energy and the emerging concept of micro-grid system raises challenges to the high power conversion techniques. Multilevel converter plays the key role in such applications and is studied in detail in the dissertation. The topologies and modulation techniques for multilevel converter are categorized at first by a thorough literature survey. The pros and cons for various multilevel topologies and modulation techniques are discussed. The 3-level neutral point clamped (NPC) topology is selected to build a 200kVA, 20 kHz power conversion system. The modularized phase leg building block of the converter is carefully designed to achieve low loss and stress for high frequency and high power operation. The switching characteristics for all the commutation loops of 3-level phase leg are evaluated by double pulse tests. The switching performance is optimized for loss and stress tradeoff. A detailed loss model is built for system loss distribution and loss breakdown calculation. Loss and stress for the phase leg and 3-phase system are quantified at all power factors. The space vector modulation (SVM) for 3-level NPC converter is investigated to achieve loss reduction, neutral voltage balance and noise reduction. The loss model and simulation model provides a quantitative analysis for loss and neutral voltage ripple tradeoff. An improved SVM method is proposed to reduce NP imbalance and switching loss simultaneously. This method also ensures an evenly distributed device loss in each phase leg and gives a constant system efficiency under different power factors. Based on the improved modulation strategy, a new modulation scheme is then proposed with largely reduced conduction loss and switching stress. Moreover, the device loss and stress distribution on a phase leg is more even. This scheme also features on the simplified implementation. The improved switching characteristics for the proposed method are verified by double pulse tests. Also the system loss breakdown and the phase leg loss distribution analysis shows the loss reduction and redistribution result. The harmonic filter for the grid interface converter is designed with LCL topology. A detailed inductor current ripple analysis derives the maximum inductor current ripple and the ripple distribution in a line cycle. The inverter side inductor is designed with the optimum loss and size trade-off. The grid side inductor is designed based on grid code attenuation requirement. Different damping circuits for LCL filter are evaluated in detail. The filter design is verified by both simulation and hardware experiment. The average model for the 3-level NPC converter and its equivalent circuit is derived with the consideration of damping circuit in both ABC and d-q frame. The modeling and control loop design is verified by transfer function measurement on real hardware. The control loops design is also tested and verified on real hardware. The interleaved DC/DC chopper is introduced at last. The different interleaving methods and their current ripple are analyzed in detail with the coupled and non-coupled inductor. An integrated coupled inductor based on 3-dimentional core structure is proposed to achieve high power density and provide both CM and DM impedance for the inductor current and output current. / Ph. D.

Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.

A method for high performance output voltage control of a four-leg inverter based three-phase transformerless UPS is proposed. Voltage control loop is employed and the method employs stationary frame resonant filter controllers for the fundamental and harmonic frequency components. A capacitor current feedback loop provides active damping and enhances the output voltage dynamic performance. The controller design and implementation details are given. Linear and nonlinear loads for balanced and unbalanced load operating conditions are considered. The steadystate and dynamic performance of the UPS are investigated in detail. A scalar PWM method with implementation simplicity and high performance is proposed and implemented. The control and PWM methods are proven by means of theory, simulations, and experiments.