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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
21

On the complexity of concentrators and multi-stage interconnection networks in switching systems. / CUHK electronic theses & dissertations collection

January 2000 (has links)
Hui Li. / "May 2000." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (p. 135-144). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.
22

Implementation considerations of algebraic switching fabrics. / CUHK electronic theses & dissertations collection

January 2002 (has links)
by Zhu Jian. / "May 2002." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (p. 162-170). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.
23

BMSN and SpiderNet as large scale ATM switch interconnection architectures.

January 1997 (has links)
by Kin-Yu Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 64-[68]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Multistage Interconnection Architectures --- p.2 / Chapter 1.2 --- Interconnection Topologies --- p.4 / Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7 / Chapter 1.4 --- Organization --- p.8 / Chapter 1.5 --- Publication --- p.9 / Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Architecture --- p.14 / Chapter 2.2.1 --- Topology --- p.14 / Chapter 2.2.2 --- Switch Modules --- p.15 / Chapter 2.3 --- Routing --- p.17 / Chapter 2.3.1 --- VP/VC Routing --- p.18 / Chapter 2.3.2 --- VP/VC Routing Control --- p.22 / Chapter 2.3.3 --- Cell Routing --- p.23 / Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24 / Chapter 2.4 --- SpiderNet --- p.25 / Chapter 2.5 --- Performance and Discussion --- p.26 / Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26 / Chapter 2.5.2 --- Network Capacity --- p.29 / Chapter 2.6 --- Concluding Remarks --- p.30 / Chapter 3 --- Multichannel ATM Switching --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Switch Design --- p.40 / Chapter 3.3 --- Channel Allocation Algorithms --- p.41 / Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41 / Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43 / Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50 / Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51 / Chapter 3.4 --- Performance and Discussion --- p.53 / Chapter 3.5 --- Concluding Remarks --- p.57 / Chapter 4 --- Conclusion --- p.62 / Bibliography --- p.64
24

Routing algorithm for multirate circuit switching in quantized Clos network.

January 1997 (has links)
by Wai-Hung Kwok. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Preliminaries - Routing in Classical Circuit Switching Clos Net- work --- p.9 / Chapter 2.1 --- Formulation of route assignment as bipartite multigraph coloring problem --- p.10 / Chapter 2.1.1 --- Definitions --- p.10 / Chapter 2.1.2 --- Problem formulation --- p.11 / Chapter 2.2 --- Edge-coloring of bipartite graph --- p.12 / Chapter 2.3 --- Routing algorithm - Paull's matrix --- p.15 / Chapter 3 --- Principle of Routing Algorithm --- p.18 / Chapter 3.1 --- Definitions --- p.18 / Chapter 3.1.1 --- Bandwidth quantization --- p.18 / Chapter 3.1.2 --- Connection splitting --- p.20 / Chapter 3.2 --- Non-blocking conditions --- p.20 / Chapter 3.2.1 --- Rearrangeably non-blocking condition --- p.21 / Chapter 3.2.2 --- Strictly non-blocking condition --- p.22 / Chapter 3.3 --- Formulation of route assignment as weighted bipartite multigraph coloring problem --- p.23 / Chapter 3.4 --- Edge-coloring of weighted bipartite multigraph with edge splitting --- p.25 / Chapter 3.4.1 --- Procedures --- p.25 / Chapter 3.4.2 --- Example --- p.27 / Chapter 3.4.3 --- Validity of the color rearrangement procedure --- p.29 / Chapter 4 --- Routing Algorithm --- p.32 / Chapter 4.1 --- Capacity allocation matrix --- p.32 / Chapter 4.2 --- Connection setup --- p.34 / Chapter 4.2.1 --- Non-splitting stage --- p.35 / Chapter 4.2.2 --- Splitting stage --- p.36 / Chapter 4.2.3 --- Recursive rearrangement stage --- p.37 / Chapter 4.3 --- Connection release --- p.40 / Chapter 4.4 --- Realization of route assignment in packet level --- p.42 / Chapter 5 --- Performance Studies --- p.45 / Chapter 5.1 --- External blocking probability --- p.45 / Chapter 5.1.1 --- Reduced load approximation --- p.46 / Chapter 5.1.2 --- Comparison of external blocking probabilities --- p.48 / Chapter 5.2 --- Connection splitting probability --- p.50 / Chapter 5.3 --- Recursive rearrangement probability --- p.50 / Chapter 6 --- Conclusions --- p.52
25

Path switching over multirate Benes network.

January 2003 (has links)
Mui Sze Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 62-65). / Abstracts in English and Chinese. / Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Evolution of Multirate Networks --- p.2 / Chapter 1.2 --- Some Results from Previous Work --- p.2 / Chapter 1.3 --- Multirate Traffic on Benes Network --- p.5 / Chapter 1.4 --- Organization --- p.7 / Chapter 2. --- Background Knowledge on Benes Network and Path Switching --- p.8 / Chapter 2.1 --- Benes Network --- p.9 / Chapter 2.1.1 --- Construction of Large Switching Fabrics --- p.9 / Chapter 2.1.2 --- Routing in Benes Network --- p.11 / Chapter 2.1.3 --- Performance when Operated as a Large Switch Fabric --- p.13 / Chapter 2.2 --- Path Switching --- p.14 / Chapter 2.2.1 --- Basic Concept of Path Switching --- p.14 / Chapter 2.2.2 --- Capacity Allocation and Route Assignment --- p.15 / Chapter 3. --- Path Switching over Benes Network --- p.20 / Chapter 3.1 --- The Model of path-switched Benes Network --- p.21 / Chapter 3.2 --- Module-to-Module Implementation --- p.21 / Chapter 3.2.1 --- The First Stage (Input Module) --- p.22 / Chapter 3.2.2 --- The Middle Stage (Central Module) --- p.23 / Chapter 3.2.3 --- The Last Stage (Output Module) --- p.24 / Chapter 3.3 --- Port-to-Port Implementation --- p.24 / Chapter 3.3.1 --- Uniform Traffic --- p.25 / Chapter 3.3.2 --- Mult irate Traffic --- p.26 / Chapter 3.4 --- Closing remarks --- p.29 / Chapter 4. --- Performance Analysis --- p.31 / Chapter 4.1 --- Traffic Constraints and Perform- ance Guarantees --- p.32 / Chapter 4.1.1 --- Arrival Curve and Service Curve --- p.33 / Chapter 4.1.2 --- Delay Bound and Backlog Bound --- p.36 / Chapter 4.2 --- Service Guarantees --- p.39 / Chapter 4.3 --- Deterministic Bounds --- p.42 / Chapter 4.3.1 --- Delay --- p.42 / Chapter 4.3.2 --- Backlog at Input Module --- p.44 / Chapter 4.3.3 --- Backlog at Output Module --- p.47 / Chapter 5. --- Simulation Results --- p.52 / Chapter 5.1 --- Uniform Traffic --- p.53 / Chapter 5.2 --- Multirate Traffic --- p.55 / Chapter 6. --- Conclusions and Future Research --- p.59 / Chapter 6.1 --- Suggestions for future research --- p.61 / Bibliography --- p.62
26

Reconfiguration issues in a quasi-static packet switch.

January 2003 (has links)
by Man Wai-Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 62-66). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- General Types of Switch Architecture --- p.2 / Chapter 1.1.1 --- Input-Buffered Switch --- p.2 / Chapter 1.1.2 --- Output-Buffered Switch --- p.4 / Chapter 1.1.3 --- Crossbar-Based Switch --- p.4 / Chapter 1.1.4 --- Shared Buffer Memory Switch --- p.5 / Chapter 1.2 --- From Clos Network to Cross-path Switch --- p.6 / Chapter 1.3 --- Motivation and Organization --- p.12 / Chapter 2 --- Route Reconfiguration in Clos Network --- p.14 / Chapter 2.1 --- Connection Matrix in Clos Network --- p.15 / Chapter 2.2 --- Rearranging Central Modules in Clos Network --- p.18 / Chapter 2.3 --- Changing the Connection Matrix --- p.20 / Chapter 2.4 --- One Step Route Reconfiguration --- p.21 / Chapter 2.5 --- Closing Remarks --- p.25 / Chapter 3. --- Frame-Based Reconfiguration Scheme in Cross-Path Switch --- p.26 / Chapter 3.1 --- Route Assignment in Cross-Path Switch --- p.27 / Chapter 3.1.1 --- Requirement Matrix and Capacity Matrix --- p.27 / Chapter 3.1.2 --- Allocation Vector --- p.29 / Chapter 3.2 --- Progress Tracing in Cross-Path Switch --- p.30 / Chapter 3.3 --- Implementing Frame-Based Reconfiguration --- p.32 / Chapter 3.3.1 --- Recognizing Receiver Virtual Path --- p.33 / Chapter 3.3.2 --- Finding Donor Virtual Path --- p.34 / Chapter 3.4 --- Simulation Results --- p.36 / Chapter 3.4.1 --- Fixed Requirement Matrix --- p.36 / Chapter 3.4.2 --- Time-Varying Requirement Matrix --- p.38 / Chapter 3.5 --- Unfavourable Reconfigurations --- p.39 / Chapter 3.6 --- Closing Remarks --- p.41 / Chapter 4. --- Performance and Delay Tradeoff in Frame-Based Reconfiguration Scheme --- p.43 / Chapter 4.1 --- Service Curve and Cross-Path Switch --- p.44 / Chapter 4.2 --- Service Curve of Cross-Path Switch under Reconfiguration --- p.45 / Chapter 4.3 --- Impact of Reconfiguration Algorithms to Maximum Delay Increase --- p.48 / Chapter 4.4 --- Numerical Example --- p.56 / Chapter 4.5 --- Closing Remarks --- p.57 / Chapter 5. --- Conclusions and Future Researches --- p.59 / Chapter 5.1 --- Suggestions for Future Researches --- p.60 / Bibliography --- p.62
27

Location management and level switching schemes in multitier mobile communication systems

Ng, Chi-kwong, 吳志光 January 2005 (has links)
published_or_final_version / abstract / toc / Computer Science / Doctoral / Doctor of Philosophy
28

Design, analysis, and implementation of multi-port refraction based electro-optic switches

Zuo, Yiying, 1974- January 2006 (has links)
Electro-optic (EO) beam deflectors are voltage-controlled devices widely used for scanning and switching applications. For example, high-speed, low-loss optical switches aimed at future optical networks can be built on EO deflectors. Novel EO deflectors distinguish themselves with a much-improved steering performance, high-speed response and simple fabrication requirements. Patterned ferroelectric crystals such as LiTaO3 are first poled to provide the required prism shaped domain structures. The application of an electrical field across the entire crystal can then be used to drive the trajectory of the beam as it travels through the poled wafer. The electric field induces an index change of opposite magnitude on the adjacent domain regions in the EO device, causing the optical beam to refract at the interfaces. / Although rectangular geometry is extensively employed in EO devices, nonrectangular scanners have demonstrated better deflection performance. Two new nonrectangular geometries capable of further enhancing the deflection performance of EO beam scanners, proposed in this dissertation, were constructed. Their parabola and half-horn geometries provide 2-3 degrees of steering, which is 2-3 times greater than the steering provided by rectangular deflectors. / EO deflectors based on the parabola and the half-horn geometries, which can provide larger deflection angles, were built. These devices demonstrated a deflection angle of 3.1°, less than 5 dB of insertion loss from fiber to fiber, and -40 dB of crosstalk. / Two packaged optical switches using rectangular EO deflectors were demonstrated. By combining these EO deflectors with fiber collimators and high voltage packaging, high speed optical switches were built and characterized. The switch design was based on a 500mum z-cut LiTaO3 single crystal wafer fabricated using the domain inversion method. The 1x2 switch had a maximum deflection angle of 1.22° with an applied voltage of 1.1 kV and the 1x4 switch had a maximum deviation angle of 2.14°, with an applied voltage of 1 kV. The average insertion loss and crosstalk figures were 2.36 dB and -36 dB, respectively. The worst case switching time was 86 ns.
29

ADSL system enhancement with multiuser detection

Chu, Liang 08 1900 (has links)
No description available.
30

A Study of Approximate Descriptions of a Random Evolution

Koepke, Henrike 23 August 2013 (has links)
We consider a dynamical system that undergoes frequent random switches according to Markovian laws between different states and where the associated transition rates change with the position of the system. These systems are called random evolutions; in engineering they are also known as stochastic switching systems. Since these kinds of dynamical systems combine deterministic and stochastic features, they are used for modelling in a variety of fields including biology, economics and communication networks. However, to gather information on future states, it is useful to search for alternative descriptions of this system. In this thesis, we present and study a partial differential equation of Fokker-Planck type and a stochastic differential equation that both serve as approximations of a random evolution. Furthermore, we establish a link between the two differential equations and conclude our analysis on the approximations of the random evolution with a numerical case study. / Graduate / 0405 / henrikek@uvic.ca

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