An Zhuo. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 62-65). / Abstracts in English and Chinese. / Acknowledgments --- p.i / 摘要 --- p.ii / Abstract --- p.iii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Circuit switching and Packet switching --- p.2 / Chapter 1.2 --- Virtual paths in high-speed networks --- p.6 / Chapter 1.3 --- BEF in cross-path switch --- p.8 / Chapter 1.4 --- Organization --- p.11 / Chapter Chapter 2 --- Analysis models --- p.12 / Chapter 2.1 --- Routing schemes in Clos network --- p.12 / Chapter 2.2 --- Path Switching --- p.15 / Chapter 2.3 --- Traffic Model of Input Modules --- p.17 / Chapter 2.4 --- Traffic Model of Output Modules --- p.19 / Chapter 2.5 --- Summary --- p.23 / Chapter Chapter 3 --- Throughput Performance of Input Modules in Path Switching --- p.24 / Chapter 3.1 --- Throughput performance vs. BEF --- p.24 / Chapter 3.2 --- Throughput performance vs. number of virtual paths --- p.30 / Chapter 3.2.1 --- Throughput performance vs. integer group size m/k --- p.33 / Chapter 3.2.2 --- Throughput performance vs. group size 0<R<2 --- p.39 / Chapter 3.2.3 --- Throughput performance vs. look-ahead scheme window size ω --- p.46 / Chapter 3.3 --- Summary --- p.48 / Chapter Chapter 4 --- Traffic Balancing Control in Path Switching --- p.50 / Chapter 4.1 --- Loss Probability in Output Modules --- p.50 / Chapter 4.1.1 --- Loss probability vs. number of central modules m --- p.51 / Chapter 4.1.2 --- Loss probability vs. knockout group size R and cluster size g --- p.52 / Chapter 4.2 --- Simulation Comparison of look-ahead scheme --- p.53 / Chapter 4.3 --- Simulation result of throughput vs. BEF --- p.55 / Chapter 4.4 --- Traffic Balancing Control --- p.55 / Chapter 4.5 --- Summary --- p.53 / Chapter Chapter 5 --- Conclusion --- p.60 / Bibliography --- p.62

by Vincent Wing-Shing Tse. / Thesis submitted in: December 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 62-[64]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Principles of Multirate Circuit Switching in Quantized Clos Network --- p.10 / Chapter 2.1 --- Formulation of Multirate Circuit Switching --- p.11 / Chapter 2.2 --- Call Level Routing in Quantized Clos Network --- p.12 / Chapter 2.3 --- Cell Level Routing in Quantized Clos Network --- p.16 / Chapter 2.3.1 --- Traffic Behavior in ATM Network --- p.17 / Chapter 2.3.2 --- Time Division Multiplexing in Multirate Circuit Switching and Cell-level Switching in ATM Network --- p.19 / Chapter 2.3.3 --- Cell Transmission Scheduling --- p.20 / Chapter 2.3.4 --- Capacity Allocation and Route Assignment at Cell-level --- p.29 / Chapter 3 --- Performance Evaluation of Different Implementation Schemes --- p.31 / Chapter 3.1 --- Global Control and Distributed Switching --- p.32 / Chapter 3.2 --- Implementation Schemes of Quantized Clos Network --- p.33 / Chapter 3.2.1 --- Classification of Switch Modules --- p.33 / Chapter 3.2.2 --- Bufferless Switch Modules Construction Scheme --- p.38 / Chapter 3.2.3 --- Buffered Switch Modules Construction Scheme --- p.42 / Chapter 3.3 --- Complexity Comparison --- p.44 / Chapter 3.4 --- Delay Performance of The Two Implementation Schemes --- p.47 / Chapter 3.4.1 --- Assumption --- p.47 / Chapter 3.4.2 --- Simulation Result --- p.50 / Chapter 4 --- Conclusions --- p.59 / Bibliography --- p.62

Microfiche copy available in the Institute Archives and Barker Engineering Library. / Vita. / Thesis (Ph. D.)--Massachusetts Institute of Technology. Dept. of Engineering and Computer Science, 1977. / Includes bibliographical references. / by John Ippocratis Capetanakis. / Ph.D.

by Chan Man Chi. / "June 2000." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (p. 150-[160]). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Hui Li. / "May 2000." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (p. 135-144). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web.

by Zhu Jian. / "May 2002." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (p. 162-170). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

by Kin-Yu Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 64-[68]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Multistage Interconnection Architectures --- p.2 / Chapter 1.2 --- Interconnection Topologies --- p.4 / Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7 / Chapter 1.4 --- Organization --- p.8 / Chapter 1.5 --- Publication --- p.9 / Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Architecture --- p.14 / Chapter 2.2.1 --- Topology --- p.14 / Chapter 2.2.2 --- Switch Modules --- p.15 / Chapter 2.3 --- Routing --- p.17 / Chapter 2.3.1 --- VP/VC Routing --- p.18 / Chapter 2.3.2 --- VP/VC Routing Control --- p.22 / Chapter 2.3.3 --- Cell Routing --- p.23 / Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24 / Chapter 2.4 --- SpiderNet --- p.25 / Chapter 2.5 --- Performance and Discussion --- p.26 / Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26 / Chapter 2.5.2 --- Network Capacity --- p.29 / Chapter 2.6 --- Concluding Remarks --- p.30 / Chapter 3 --- Multichannel ATM Switching --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Switch Design --- p.40 / Chapter 3.3 --- Channel Allocation Algorithms --- p.41 / Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41 / Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43 / Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50 / Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51 / Chapter 3.4 --- Performance and Discussion --- p.53 / Chapter 3.5 --- Concluding Remarks --- p.57 / Chapter 4 --- Conclusion --- p.62 / Bibliography --- p.64

by Wai-Hung Kwok. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Preliminaries - Routing in Classical Circuit Switching Clos Net- work --- p.9 / Chapter 2.1 --- Formulation of route assignment as bipartite multigraph coloring problem --- p.10 / Chapter 2.1.1 --- Definitions --- p.10 / Chapter 2.1.2 --- Problem formulation --- p.11 / Chapter 2.2 --- Edge-coloring of bipartite graph --- p.12 / Chapter 2.3 --- Routing algorithm - Paull's matrix --- p.15 / Chapter 3 --- Principle of Routing Algorithm --- p.18 / Chapter 3.1 --- Definitions --- p.18 / Chapter 3.1.1 --- Bandwidth quantization --- p.18 / Chapter 3.1.2 --- Connection splitting --- p.20 / Chapter 3.2 --- Non-blocking conditions --- p.20 / Chapter 3.2.1 --- Rearrangeably non-blocking condition --- p.21 / Chapter 3.2.2 --- Strictly non-blocking condition --- p.22 / Chapter 3.3 --- Formulation of route assignment as weighted bipartite multigraph coloring problem --- p.23 / Chapter 3.4 --- Edge-coloring of weighted bipartite multigraph with edge splitting --- p.25 / Chapter 3.4.1 --- Procedures --- p.25 / Chapter 3.4.2 --- Example --- p.27 / Chapter 3.4.3 --- Validity of the color rearrangement procedure --- p.29 / Chapter 4 --- Routing Algorithm --- p.32 / Chapter 4.1 --- Capacity allocation matrix --- p.32 / Chapter 4.2 --- Connection setup --- p.34 / Chapter 4.2.1 --- Non-splitting stage --- p.35 / Chapter 4.2.2 --- Splitting stage --- p.36 / Chapter 4.2.3 --- Recursive rearrangement stage --- p.37 / Chapter 4.3 --- Connection release --- p.40 / Chapter 4.4 --- Realization of route assignment in packet level --- p.42 / Chapter 5 --- Performance Studies --- p.45 / Chapter 5.1 --- External blocking probability --- p.45 / Chapter 5.1.1 --- Reduced load approximation --- p.46 / Chapter 5.1.2 --- Comparison of external blocking probabilities --- p.48 / Chapter 5.2 --- Connection splitting probability --- p.50 / Chapter 5.3 --- Recursive rearrangement probability --- p.50 / Chapter 6 --- Conclusions --- p.52

Mui Sze Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 62-65). / Abstracts in English and Chinese. / Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Evolution of Multirate Networks --- p.2 / Chapter 1.2 --- Some Results from Previous Work --- p.2 / Chapter 1.3 --- Multirate Traffic on Benes Network --- p.5 / Chapter 1.4 --- Organization --- p.7 / Chapter 2. --- Background Knowledge on Benes Network and Path Switching --- p.8 / Chapter 2.1 --- Benes Network --- p.9 / Chapter 2.1.1 --- Construction of Large Switching Fabrics --- p.9 / Chapter 2.1.2 --- Routing in Benes Network --- p.11 / Chapter 2.1.3 --- Performance when Operated as a Large Switch Fabric --- p.13 / Chapter 2.2 --- Path Switching --- p.14 / Chapter 2.2.1 --- Basic Concept of Path Switching --- p.14 / Chapter 2.2.2 --- Capacity Allocation and Route Assignment --- p.15 / Chapter 3. --- Path Switching over Benes Network --- p.20 / Chapter 3.1 --- The Model of path-switched Benes Network --- p.21 / Chapter 3.2 --- Module-to-Module Implementation --- p.21 / Chapter 3.2.1 --- The First Stage (Input Module) --- p.22 / Chapter 3.2.2 --- The Middle Stage (Central Module) --- p.23 / Chapter 3.2.3 --- The Last Stage (Output Module) --- p.24 / Chapter 3.3 --- Port-to-Port Implementation --- p.24 / Chapter 3.3.1 --- Uniform Traffic --- p.25 / Chapter 3.3.2 --- Mult irate Traffic --- p.26 / Chapter 3.4 --- Closing remarks --- p.29 / Chapter 4. --- Performance Analysis --- p.31 / Chapter 4.1 --- Traffic Constraints and Perform- ance Guarantees --- p.32 / Chapter 4.1.1 --- Arrival Curve and Service Curve --- p.33 / Chapter 4.1.2 --- Delay Bound and Backlog Bound --- p.36 / Chapter 4.2 --- Service Guarantees --- p.39 / Chapter 4.3 --- Deterministic Bounds --- p.42 / Chapter 4.3.1 --- Delay --- p.42 / Chapter 4.3.2 --- Backlog at Input Module --- p.44 / Chapter 4.3.3 --- Backlog at Output Module --- p.47 / Chapter 5. --- Simulation Results --- p.52 / Chapter 5.1 --- Uniform Traffic --- p.53 / Chapter 5.2 --- Multirate Traffic --- p.55 / Chapter 6. --- Conclusions and Future Research --- p.59 / Chapter 6.1 --- Suggestions for future research --- p.61 / Bibliography --- p.62

by Man Wai-Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 62-66). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- General Types of Switch Architecture --- p.2 / Chapter 1.1.1 --- Input-Buffered Switch --- p.2 / Chapter 1.1.2 --- Output-Buffered Switch --- p.4 / Chapter 1.1.3 --- Crossbar-Based Switch --- p.4 / Chapter 1.1.4 --- Shared Buffer Memory Switch --- p.5 / Chapter 1.2 --- From Clos Network to Cross-path Switch --- p.6 / Chapter 1.3 --- Motivation and Organization --- p.12 / Chapter 2 --- Route Reconfiguration in Clos Network --- p.14 / Chapter 2.1 --- Connection Matrix in Clos Network --- p.15 / Chapter 2.2 --- Rearranging Central Modules in Clos Network --- p.18 / Chapter 2.3 --- Changing the Connection Matrix --- p.20 / Chapter 2.4 --- One Step Route Reconfiguration --- p.21 / Chapter 2.5 --- Closing Remarks --- p.25 / Chapter 3. --- Frame-Based Reconfiguration Scheme in Cross-Path Switch --- p.26 / Chapter 3.1 --- Route Assignment in Cross-Path Switch --- p.27 / Chapter 3.1.1 --- Requirement Matrix and Capacity Matrix --- p.27 / Chapter 3.1.2 --- Allocation Vector --- p.29 / Chapter 3.2 --- Progress Tracing in Cross-Path Switch --- p.30 / Chapter 3.3 --- Implementing Frame-Based Reconfiguration --- p.32 / Chapter 3.3.1 --- Recognizing Receiver Virtual Path --- p.33 / Chapter 3.3.2 --- Finding Donor Virtual Path --- p.34 / Chapter 3.4 --- Simulation Results --- p.36 / Chapter 3.4.1 --- Fixed Requirement Matrix --- p.36 / Chapter 3.4.2 --- Time-Varying Requirement Matrix --- p.38 / Chapter 3.5 --- Unfavourable Reconfigurations --- p.39 / Chapter 3.6 --- Closing Remarks --- p.41 / Chapter 4. --- Performance and Delay Tradeoff in Frame-Based Reconfiguration Scheme --- p.43 / Chapter 4.1 --- Service Curve and Cross-Path Switch --- p.44 / Chapter 4.2 --- Service Curve of Cross-Path Switch under Reconfiguration --- p.45 / Chapter 4.3 --- Impact of Reconfiguration Algorithms to Maximum Delay Increase --- p.48 / Chapter 4.4 --- Numerical Example --- p.56 / Chapter 4.5 --- Closing Remarks --- p.57 / Chapter 5. --- Conclusions and Future Researches --- p.59 / Chapter 5.1 --- Suggestions for Future Researches --- p.60 / Bibliography --- p.62