Output queues in network switches are known to provide a suitable architecture for scheduling disciplines that need to provide quality of service (QoS) guarantees. However, today’s memory technology is incapable of meeting the speed requirements. Combined input and output queued (CIOQ) switches have emerged as one alternative to address the problem of memory speed. When a switch of this architecture uses a stable matching algorithm to transfer packets across the switch fabric, an output queued (OQ) switch can be mimicked exactly with a speedup of only two. The use of a stable matching algorithm typically requires complex and time-consuming calculations to ensure the behaviour of an OQ switch is maintained. Stable matching algorithms are well studied in the area in which they originally appeared. However, little is presently known on how the stable matching algorithm performs in CIOQ switches and how key parameters are affected by switch size, traffic type and traffic load. Knowledge of how these conditions affect performance is essential to judge the practicability of an architecture and to provide useful information on how to design such switches. Until now, CIOQ switches were likely to be dismissed due to the high complexity of the stable matching algorithm when applied to other applications. However, the characteristics of a stable matching algorithm in a CIOQ switch have not been thoroughly analysed. The principal goal of this thesis is to identify the conditions the stable matching algorithm encounters in a CIOQ switch under realistic operational scenarios. This thesis provides accurate mathematical models based on Markov chains to predict the value of key parameters that affect the complexity and runtime of a stable matching algorithm in CIOQ switches. The applicability of the models is then backed up by simulations. The results of the analysis quantify critical operational parameters, such as the size and number of preference lists and runtime complexity. These provide detailed insights into switch behaviour and useful information for switch designs. Major conclusions to be drawn from this analysis include that the average values of the key parameters of the stable matching algorithm are feasibly small and do not strongly correlate with switch size, which is contrary to the behaviour of the stable matching ii algorithm in its original application. Furthermore, although these parameters have wide theoretical ranges, the mean values and standard deviations are found to be small under operational conditions. The results also suggest that the implementation becomes very versatile as the completion time of the stable matching algorithm is not strongly correlated to the network traffic type; that is, the runtime is minimally affected by the nature of the traffic.

The growing acceptance of B-ISDN (Broadband Integrated Services Digital Network) requires entirely new switching support a wide range of service demands including voice, video and data. At the same time, advances in the field of VLSI have enabled new principles to the design and architecture high-performance switching fabrics. Direct binary switch fabrics are a suitable candidate for future B- switches. Binary hypercubes have regular topology, are highly fault and have multiple paths for routing cells which help avoid performance penalties due to congestion and faults. In addition, these switches can adopt the novel, distributed, and adaptive routing scheme called 'deflection routing'. In normal routing, cells are routed along shortest paths to their destinations; in case of multiple cells contending for a single outgoing channel, the rest of the contending cells are either buffered or dropped to avoid congestion. In the case of deflection routing, cells can be routed along non-shortest paths. As a result, deflection routing helps avoid dropping cells. The scheme may be implemented with and without queuing buffers at the routers. In order to properly provision, control, and design these hypercube switches, it is essential that their performance capabilities be completely understood. Researchers have used both analytical model and simulations to evaluate performance of hypercube switches. The presence of distributed logic, multi-path routing, deflection routing, and queuing buffers make modeling tasks highly challenging. Building a reasonably accurate model of a hypercube switch with queuing buffers and deflection routing and using that model to gain practical insights into some of the important design parameters of the switch has been the major motivation of this thesis. An approximate Markov model of a single switching element is built to capture the behavior of a d-dimension switch. The numerical model is solved iteratively. Accuracy of the model is established by validating against simulation results. One disadvantage of having multiple paths, queuing buffers, and deflection motion of cells in hypercube switches is that the cells belonging to a particular traffic stream may not be delivered at their destinations in sequence. This phenomenon is known as 'out-of-orderness' of cells. An additional goal of this thesis has been development of a model to capture out-of-orderness phenomenon. The model is validated by comparing model results against simulation. Results show that the model is accurate and reveals significant insight into switch's behavior that can be used to design and engineer d-dimension hypercube switches.

MPLS-Based Best-Effort Traffic Engineering Jerapong Rojanarowan 120 Pages Directed by Dr. Henry L. Owen The objective of this research is to develop a multipath traffic engineering framework for best-effort traffic in Multiprotocol Label Switching (MPLS) networks so as to deliver more equal shares of bandwidth to best-effort users as compared to the traditional shortest-path algorithm. The proposed framework is static and the input to the traffic engineering algorithm is restricted to network topology. Performance evaluation of this framework is conducted by simulation using ns-2 network simulator. In a multi-service capable network, some portion of the bandwidth is reserved for guaranteed services and the leftover portion is dedicated to best-effort service. This research examines the problem of traffic engineering for the remaining network bandwidth that is utilized by best-effort traffic where demands are not known a priori. This framework will result in making the limited available best-effort traffic bandwidth more equitably shared by the best-effort flows over a wide range of demands. Traditional traffic engineering research has not examined best-effort traffic.

Not available

The growth of mobile networks and the imminent deployment of third generation networks and services will require signalling networks to maintain their integrity during increased unanticipated traffic volumes. As signalling networks become larger and more complex, an analysis ofprotocol operation is necessary to determine the effectiveness of the current protocol implementation and to evaluate the applicability of the proposed enhancements. The objective of this study ,is to develop analytical models to analyse the impact of Signalling Transfer Point congestion on network performance when simple message discard schemes are used as the primary flow control mechanism, and to investigate suitable congestion and flow control mechanisms to help alleviate the congestion. Unlike previous studies, that are localised and only concentrate on the nodes around the congested entity, the models presented here examine the impact of network wide and focused overloads on the entire network. The study considers both the fixed-line and mobile network environments, and analyses the performance of the ISDN User Part and Mobile Application Part protocols. The call completion rate and location update success rate are used to measure performance, instead of message throughput, since these parameters provide a more appropriate measure of the grade-of-service and more accurately reflect the level of service provided to a customer. The steady state equilibrium models, derived here, can be used to quickly estimate the safe operating regions of a signalling network, while the transient models provide a more intuitive perspective of the traffic processes that lead to congestion . Furthermore, these models can be used to examine the network performance for different message priority schemes, routing algorithms, overload scenarios and network configurations. The performance of various congestion control mechanisms that incorporate non-linear throttling schemes is also evaluated, together with an examination of the impact of congestion on multiple user parts in a mobile network environment. Message priority schemes are found to offer little or no advantage in a fixed network environment, but in a mobile network they can be used to maintain the network's performance at an optimum level during periods of overload. Network performance is also improved if congestion controls block load-generating traffic at the initial onset of congestion and then gradually restore traffic as the performance improves . / Thesis (Ph.D.)-University of Natal, Durban, 2002.

Indiana University-Purdue University Indianapolis (IUPUI) / Multi-Protocol Label Switching (MPLS) is an emerging technology which is the initial step for the forthcoming generation of communication. It uses Labels in order to identify the packets unlike the conventional IP Routing Mechanism which uses the routing table at each router to route the packet. MPLS uses the techniques of FRR with the help of RSVP/CR-LDP to overcome the link and/or node failures in the network. On the other hand there are certain limitations/drawbacks of using the above mechanisms for Failure Detection and Recovery which are multiple protocols such as RSVP/CR-LDP over OSPF/IS-IS and complex algorithms to generate backup paths since each router works individually in order to create a backup tunnel. So to overcome the listed limitations, this paper discusses a new technique for MPLS Networks which is Source Routing \cite{48}. Source Routing is the technique in which the source plays the role of directing the packet to the destination and no other router plays the role of routing the packet in the network. Using the OPNET Modeler 17.5 tool for implementing source routing when there is a network failure is performed and the results are compared by implementing RSVP/CR-LDP over the same failed network. The comparative results show that the network performance is best in the case of Source Routing implementation as compared to the RSVP and CR-LDP signaling over the MPLS Networks.

Optical packet switching (OPS) is one of the more promising solutions for meeting the diverse needs of broadband networking applications of the future. By virtue of its small data traffic granularity as well as its nanoseconds switching speed, OPS can be used to provide connection-oriented or connectionless services for different groups of users with very different networking requirements. The optical buffer and the switch fabric are two of the most important components in an OPS router. In this research, novel designs for the optical buffer and switch fabric are proposed and experimentally demonstrated. In particular, an optical buffer that is based on a folded-path delay-line tree architecture will be discussed. This buffer is the most compact non-recirculating optical delay line buffer to date, and it uses an array of high-speed ON-OFF optical reflectors to dynamically reconfigure its delay within several nanoseconds. A major part of this research is devoted to the design and performance optimization of these high-speed reflectors. Simulations and measurements are used to compare different reflector designs as well as to determine their optimal operating conditions. Another important component in the OPS router is the switch fabric, and it is used to perform space switching for the optical packets. Optical switch fabrics are used to overcome the limitations imposed by conventional electronic switch fabrics: high power consumption and dependency on the modulation format and bit-rate of the signals. Currently, only those fabrics that are based on the broadcast-and-select architecture can provide truly non-blocking multicast services to all input ports. However, a major drawback of these fabrics is that they are implemented using a large number of optical gates based on semiconductor optical amplifiers (SOA). This results in large component count and high energy consumption. In this research, a new multicast-capable switch fabric which does not require any SOA gates is proposed. This fabric relies on a passive all-optical gate that is based on the Four-wave mixing (FWM) wavelength conversion process in a highly-nonlinear fiber. By using this new switch architecture, a significant reduction in component count can be expected.

The demand for high-performance and power scalable DSP processors for telecommunication and portable devices has increased significantly in recent years. The Fast Fourier Transform (FFT) computation is essential to such designs. This work presents a switch-based architecture to design radix-2 FFT processors. The processor employs M processing elements, 2M memory arrays and M Read Only Memories (ROMs). One processing element performs one radix-2 butterfly operation. The memory arrays are designed as single-port memory, where each has a size of N/(2M); N is the number of FFT points. Compared with a single processing element, this approach provides a speedup of M. If not addressed, memory collisions degrade the processor performance. A novel algorithm to detect and resolve the collisions is presented. When a collision is detected, a memory management operation is executed. The performance of the switch architecture can be further enhanced by pipelining the design, where each pipeline stage employs a switch component. The result is a speedup of Mlog2N compared with a single processing element performance. The utilization of single-port memory reduces the design complexities and area. Furthermore, memory arrays significantly reduce power compared with the delay elements used in some FFT processors. The switch-based architecture facilitates deactivating processing elements for power scalability. It also facilitates implementing different FFT sizes. The VLSI implementation of a non-pipeline switch-based processor is presented. Matlab simulations are conducted to analyze the performance. The timing, power and area results from RTL, synthesis and layout simulations are discussed and compared with other processors. / text

In this thesis we provide a model for a bufferless optical burst switching (OBS) and an optical packet switching (OPS) network. The thesis is divided in three parts. <p><p>In the first part we introduce the basic functionality and structure of OBS and OPS networks. We identify the blocking probability as the main performance parameter of interest. <p><p>In the second part we study the statistical properties of the traffic that will likely run through these networks. We use for this purpose a set of traffic traces obtained from the Universidad Politécnica de Catalunya. Our conclusion is that traffic entering the optical domain in future OBS/OPS networks will be long-range dependent (LRD). <p><p>In the third part we present the model for bufferless OBS/OPS networks. This model takes into account the results from the second part of the thesis concerning the LRD nature of traffic. It also takes into account specific issues concerning the functionality of a typical bufferless packet-switching network. The resulting model presents scalability problems, so we propose an approximative method to compute the blocking probability from it. We empirically evaluate the accuracy of this method, as well as its scalability. / Doctorat en Sciences de l'ingénieur / info:eu-repo/semantics/nonPublished