This diploma thesis deals with noncontact temperature measurement using luminescent materials. In the theoretical part of the thesis, luminescent materials were selected on the basis of a literature review with respect to sensitivity and operating temperature range. In the experimental part of the thesis, photoluminescence of CdSe/ZnS and GaAs quantum dots for various temperatures was measured and the relative change of luminescence parameters such as emission peak position, intensity, intensity ratio of two emission peaks, and lifetime of luminescence were determined from the measurements in agreement with expectations according to the literature. Achieving high spatial resolution would be made possible by measuring cathodoluminescence, where the luminescence spectra are obtained with an order of magnitude higher spatial resolution. These measurements and the influence of electron beam on the luminescence quality of selected materials will be subject of further experimental study.

I characterize the behavior of microcantilever arrays which utilize the in-plane photonic transduction that I've previously developed and evaluate the performance of the microcantilever arrays in simple sensing scenarios with integrated microfluidics. First the thermal responses of microcantilevers with a variety of patterns of deposited gold films are compared. Using a scanning electron microscope, I observe the deflection thermal sensitivities of 300 µm long microcantilevers to be -170.82 nm/K for a full gold coating and -1.93 nm/K for no gold coating. Using the photonic transduction method I measure a thermal sensitivity of -1.46 nm/K for a microcantilever array with no gold. A microcantilever array integrated with microfluidics is exposed to a solution of bovine serum albumin (BSA) followed by solutions of various pH's. In all cases I observe a previously unreported transient deflection response. We find that the transient response is due to temporary nonuniform concentration distributions. In response to nonspecific binding of BSA, I observe a transient surface stress of -0.23 mN/m that agrees well with the -0.225 mN/m predicted by simulations. We hypothesize that the deflection response to pH changes is due to stress generated by conformational changes of bound BSA.The deflection response of an integrated microcantilever array to different types of flow and different flow rates is observed. Simulations of the deflection response match well with experimental results but disagree at higher flow rates. For flow rates greater than 200 µL/min, the limitation of the differential signal's dynamic range becomes apparent. We then investigate flow driven by an on-chip reciprocating reservoir pump. We demonstrate that it is possible to use the reciprocating pump to achieve high flow rates while making deflection measurements in-between reservoir actuations. Investigations of the microcantilever array noise show that flicker noise dominates below 10 Hz, while above 10 Hz, readout noise dominates. A minimum deflection noise density of 15 pW/√Hz is achieved. To improve the signal-to-noise ratio I develop algorithms for a digital lock-in amplifier with a digital phase-lock loop. In simulation the lock-in amplifier is able to improve the SNR by up to a factor of 6000, and self-lock to a noisy carrier signal without an external reference signal.

Chemotherapy Induced Peripheral Neuropathy (CIPN) is known to impact negatively on patients' quality of life. It has been reported that these patients tend to have sensitivity thresholds to stimuli, such as pain and temperature, that are different from those of normal subjects. The effect of chemotherapeutic agents on the central nervous system (CNS) has been observed; however, most of the mechanisms involved are not exactly understood. A quantitative investigation into the temperature sensitivity changes in the spinal cords and brains of chemotherapy patients would provide important information in understanding the side effects of this treatment modality. In the first part of the project, the temperature perceptional changes in terms of brain activation patterns of the chemotherapy patients with CIPN are studied using brain function MRI. In the second part of the project, the structural changes of the brain and spinal cord of chemotherapy patients with CIPN are studied using diffusion tensor imaging (DTI). High b-value (b = 1500 s/mm2) and low b-value (b=650 s/mm2) settings will be use during the spinal cord DTI scans. Due to the sample size limitation, no comparison between healthy volunteers and CIPN patients can be done based on the existing temperature fMRI data. However, the developed temperature fMRI protocol shows good reliability in detecting temperature response. Based on the spinal cord DTI result using b = 1500 s/mm2, decrease in FA value has been observed. The corresponding FA values of CIPN patient and healthy volunteers are 0.28±0.10 and 0.41±0.02 , respectively. (t-test = 2.63 >2.447, p=0.05 level of significant) However, no significant difference is observed in other diffusion parameters. This results also suggests that application of high b-value setting is more suitable as it is better at detecting diffusion at microstructure. / Thesis / Doctor of Philosophy (PhD)

A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C. / Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C. / Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C. / Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

La croissance du marché des pompes à chaleur contribue à l'augmentation de la thermosensibilité de la demande électrique. Il devient nécessaire de mieux comprendre l'impact des usages thermosensibles de l'électricité, notamment concernant ceux qui sont corrélés de manière non linéaire à la température extérieure. Dans cette optique, cette thèse vise à construire un cadre de modélisation qui permette i) d'analyser les facteurs d'influence de la thermosensibilité à partir d'une description physique des usages thermosensibles, et ii) de réaliser des diagnostics de ces paramètres d'influence tout en tenant compte des incertitudes associées. Une approche de modélisation hybride qui bénéficie des avantages de modèles statistiques et de modèles physiques est principalement employée pour répondre à ces questions.La première étape consiste à estimer la part thermosensible de la demande réelle par un modèle prédictif top-down. On développe ensuite un modèle d'analyse physique de la thermosensibilité à l'échelle régionale à partir de la thermique du bâtiment. On s'appuie notamment sur des modèles pseudo-physiques de performance de pompes à chaleur qui sont régressés sur des données constructeur ou des mesures de performances réelles. Un COP régional est déterminé pour l'ensemble des PAC installées. Enfin, les paramètres d'influence du modèle de thermosensibilité ainsi développé sont estimés à l'aide de l'approche bayésienne, qui offre un cadre pour le traitement de l'incertitude sous la forme de probabilités. Des coefficients équivalents de déperditions thermiques, une température intérieure équivalente ainsi que les parts du chauffage Joule et par PAC pour le parc de bâtiments régional ont été obtenus. / The growing heat pump market contributes to the increase in temperature sensitivity of electricity demand. It becomes necessary to understand the impact of temperature sensitive end-uses of electricity, including those which are correlated non-linearly to the outside temperature. In this context, this thesis aims to build a modeling framework to i) analyze the influencing factors of the temperature sensitivity of electricity demand from a physical description of temperature-sensitive equipment, and ii) to perform diagnoses of these parameters of influence by taking into account the associated uncertainties. A hybrid modeling approach that benefits the advantages of statistical models and physical models is used to answer these questions.Firstly, the temperature-sensitive part of electricity demand is estimated by a predictive top-down model. Then a physical model to analyze the temperature sensitivity at regional level is developed based on building thermal energy needs. A regional coefficient of performance (COP) is determined for the whole installed heat pumps by using pseudo-physical models which are regressed on manufacturer data or actual performance measures. Finally, the parameters of influence of the developed temperature sensitivity model are estimated using the Bayesian approach which provides a framework for the treatment of uncertainty in the form of probabilities. Equivalent coefficients of heat loss, an equivalent internal temperature, as well as the share of Joule heating and the share of heat pumps for the regional building stock are obtained.

Le procédé de soudage laser est largement utilisé dans les travaux d'assemblage, en particulier, dans ledomaine de l'industrie automobile. L'acier dual phase DP600 est un acier à haute résistance qui permet deréduire le poids de l'automobile dans le cadre de l'allègement des structures. Notre travail s' estessentiellement basé sur l'évaluation des contraintes résiduelles générées dans l'acier DP600 lors du soudagepar laser. Deux approches ont été réalisées. L'approche expérimentale a été réalisée à l'aide de méthodes derayon X et par neutrons pour calculer les contraintes résiduelles. L'approche de simulation a été réalisée parcouplage de différentes formulations numériques.Numériquement, le formalisme de la mécanique continue a été utilisé par des simulations par éléments finis(FEM) pour analyser et évaluer les contraintes résiduelles. Sur la base de tests de traction expérimentaux, lemodèle constitutif élasto-thermo-plastique de l'acier DP600 a été identifié. L'écrouissage du matériau a étéétudié par la loi de Ludwik et de Voce. A partir de résultats experimentaux, un modèle a été proposé et lesrésultats analysés en utilisant une loi de mélange martensite (écrouissage Ludwik) et ferrite (adoucissementde Voce). De même, nous avons étudié la sensibilité à la température en utilisant plusieurs modèles :Johnson-Cook, Khan, Chen. A partir de cette étude, nous avons proposé un modèle de sensibilité à tatempérature. Enfin, un modèle de sensibilité à la déformation plastique, à la vitesse de déformation issu destravaux d'A.Gavrus et un modèle d'anisotropie planaire définit par la théorie de Hill ont été ajoutés.Une méthode d'automate cellulaire (CA) 2D a été programmée pour simuler l'évolution de la microstructurelors de la solification liée au processus de soudage laser. Dans ce modèle, les phénomènes de nucléationavec prise en compte de l'orientation de la croissance, de la concentration et de la vitesse de croissance àl'interface solide/liquide, l'anisotropie de la tension de surface, de la diffusion, ainsi que la fraction desphases en présence ont été pris en compte. De plus, les équations de conservation ont été étudiées en détail etanalysés. Les résultats ainsi que le champ de température issu du modèle FEM ont été importés dans lemodèle CA. En comparant la simulation et les résultats expérimentaux, de bonnes concordances ont ététrouvées.Par la suite, nous avons réalisés un couplage des deux modèles CA et FEM. Concernant le procédé laser, lesrésultats du modèle par éléments finis ont été analysés. La géométrie de l'échantillon, la source de chaleur,les conditions aux limites, le comportement thermo-mécanique de l'acier dual phase DP600 telles que laconductivité, la densité, la chaleur spécifique, l'expansion, l'élasticité et la plasticité sont introduites. Lesmodèles d'analyse du terme d'écrouissage, de la sensibilité à la vitesse de déformation, de la sensibilité à latempérature, de l'anisotropie plastique et de l'anisotropie élastique ont été simulés. Les fractions volumiquesconcernant ta nature des deux phases en présence ont été également étudiées.Les résultats numériques finaux tes contraintes résiduelles ont été étudiées. Les comparaisons avec desmesures experimentales ont montré à la fois quels phénomènes étudiés sont prépondérants et tes effets moinsinfluents sur l'évaluation des contraintes résiduelles. Les résultats tes plus probants ont montré des bonnesconvergences entre l'approche numérique et expérimentale. Ces résultats confortent la robustesse du modèlenumérique developpé. / Laser welding process is widely used in assembly work of automobi le industry. DP600 dual phase steeis a high strength steel to reduce automobile weight. Residual stresses are produced during laser weldingDP600. Continuum mechanics is used for analyzing res idual stresses by finite element simulation.Based on experimental tensile tests, the DP600 steel constitutive model are identified. The hardening termaccording to Ludwik law, Voce law and a proposed synthesis model are studied. The temperature sensitivityof Johnson-Cook, Khan, Chen and a proposed temperature sensitivity model are investigated. The strain ratesensitivity model proposed by A. Gavrus and planar anisotropy defined by Hi ll theory are also used.Cellul ar Automaton (CA) 20 method are programed for the simulation of solidification microstructureevolution during laser welding process. The temperature field of CA are imported from finite element analysimodel. The analysis function of nucleation, solid fraction, interface concentration, surface tension an isotropy,diffusion, interface growth ve locity and conservation equations are presented in detail. By comparing thesimulation and experimental results, good accordances are found.Modelling by a finite element method of laser welding process are presented. Geometry of specimen, heatsource, boundary conditions, DP600 dual phase steel material properties such as conductivity, density, specifiheat, expansion, elasticity and plasticity are introduced. Models analyzing hardening term, strain ratesensitivity, temperature sensitivity, plastic an isotropy and elastic an isotropy are simulated.The numerical results of laser welding DP600 steel process are presented. The influence of hardening term,strain rate sensitivity, temperature sensitivity and anisotropy on residual stresses are analyzed. Comparisonwith experimental data show good numerical accuracy.Keywords: Laser Welding, DP600, Residual Stress, Cellular Automaton, Hardening, Temperature sensitivity,Strain Rate Sensitivity, Anisotropy, Mixture dual phase law.

Current-to-pressure (I/P) converters are pneumatic devices which provide precise control of pressure in various industries – for example these devices are often used in valve positioner systems (typically found in the oil and gas industry) and tensioning systems (typically used in the packaging industry). With an increasing demand for such devices to operate in harsh environments all by delivering acceptable performance means that Current-to-pressure converters need to be carefully designed such that environmental factors have no or minimal effects on its performance. This work presents an investigation of the principles of operation of an existing I/P converter through mathematical modelling. A simulation model has been created and which allows prediction of performance of the I/P converter. This tool has been used to identify areas of poor performances through theoretical analysis and consequently led to optimisation of certain areas of the I/P converter through a design change to deliver improved performances, for instance the average percentage shift in gain at 1mA input signal (over the temperature range of -40°C to 85°C) on the new I/P converter is 2.13% compared to the average gain of 4.24% on the existing I/P converter, which represents an improvement of almost two fold. Experimental tests on prototypes have been carried out and tests results showed that improved linearity and temperature sensitivity can be expected from the new design.

In the last 10 years, no significant increase in the peak electricity consumption of the region of Stockholm has been observed, despite new customers being connected to the grid. But, as urbanization continues and with electrification being a decisive step of decarbonization pathways, more growth is expected in the future. However, the Swedish Transmission System Operator (TSO), Svenska Kraftnat, can only supply a limited power to Stockholm region. Distribution System Operators (DSOs) such as Vattenfall Eldistribution, which operates two thirds Stockholm region's distribution grid, need to find solutions to satisfy an increasing demand with a limited power supply. In these times, forecasting the worst-case scenarios, i.e., the highest possible loads, becomes a critical question. In Sweden, peak loads are usually triggered by the coldest temperatures, but the recent winters have been mild: this brings uncertainty about a possible underlying temperature adjusted growth that would be masked by relatively warm winters. Answering the question 'What would be the highest loads in 2022 with -20°C in Stockholm region ?' could help Vattenfall Eldistribution estimating the flexibility needed nowadays and designing the future grid with the necessary grid reinforcements. This master thesis uses a data-driven approach based on eleven years of hourly data on the period 2010-2021 to investigate the temperature sensitivity of aggregated electricity load in Stockholm region. First, an exploratory analysis aims at quantifying how large the growth has been in the past ten years and at understanding how and when peak loads occur. The insights obtained help design two innovative regression techniques that investigate the evolution of the loads across years and provide first estimates of peak loads. Then, a Seasonal Autoregressive Integrated Moving Average with eXogenous regressors (SARIMAX) process is used to model a full winter of load as a function of temperatures. This third method provides new and more reliable estimates of peak loads in 2022 at e.g. -20°C. Eventually, the SARIMAX estimates are kept and a synthesis of the global outlooks of the three methods and possible extensions of the SARIMAX method is presented in a final section. The results conclude on a significant increase in the load levels in southern Stockholm ('Stockholm Sodra') between 2010 and 2015 and stable evolution onwards, while the electric consumption in Northern Stockholm remained stable during the period 2010-2021. During a very cold winter, the electricity demand is expected to exceed the subscription levels during about 300h in Stockholm Sodra and 200h in Stockholm Norra. However, this will be a rare occurrence, which suggests that short-term solutions could be privileged rather than costly grid extension work. Many questions arise, and the capability of local heat & power production and electricity prices signals to regulate today's demand are yet to investigate. Additional work exploring future demand scenarios at a smaller scale could also be contemplated. / Under den senaste årtionden har Stockholms toppkonsumtion av el inte ökat markant trots nya elkunder som ansluter till elnätet. Med en snabb urbanisering, är ökad elektrifiering en huvudlösning för att uppnå ett fossilfritt samhälle och denna trend förväntas fortsätta under kommande årtionden. Samtidigt börjar den svenska transmissionsnätoperatören (TSO) Svenska kraftnät få problem med att leverera elkraft till Stockholmsregionen, på grund av en begränsad överföringskapacitet. Därför måste lokala eldistributörer (DSO), liksom Vattenfall Eldistribution, som är Sveriges största DSO med systemansvar för distributionssystem, undersöka nya lösningar för att uppfylla den ökande efterfrågan på el. Det blir dessutom mycket viktigt att identifiera de värsta tänkbara scenario, som att göra prognos av högsta möjliga elförbrukning. Stockholm konsumerar exempelvis mest el när det är som kallast – men de senaste vintrarna har varit milda jämfört med till exempel vintrarna 2010 – 2011 eller 2012 – 2013 då temperaturer i Stockholmsregion mättes till under -20°C grader för flera dagar i sträck. Detta resulterar i en relevant frågeställning: ” Vad skulle Stockholms elkonsumtion vid -20°C bli 2021 eller 2022?”. Att kvantitativt kunna besvara denna fråga skulle hjälpa Vattenfall med att designa framtidens elnät samt se till att det finns rätt mängd flexibilitet i reserv i nuvarande Stockholm Flex elmarknad. Detta examensarbete utgår från att kvantitativt analysera denna frågeställning. Utgångsläget är ett datadrivet tillvägagångssätt baserat på tio års tidseriedata för att undersöka temperaturkänsligheten för det aggregerade elbehovet i Stockholmsregionen, och dra slutsatser om dess utveckling genom åren. I första hand, utförs en explorativ analys för att förstå när och hur toppbelastning kan hända. Då hjälper dessa insikter till att utforma två innovativa regressionsmetoder för att undersöka utvecklingen av elförbrukning under det senaste decenniet och uppskatta värdet på toppbelastningen. Därefter används ett säsongmässigt autoregressivt integrerat rörligt genomsnitt med exogena faktorer (SARIMAX) för att modellera en vinter som en funktion av temperaturerna. Denna tredje metod behandlar nya och mer tillförlitliga beräkningar av toppbelastning värden i 2022 på -20°C. Huvudslutsatser från examensarbetet är att elförbrukningen skulle öka i området Stockholm Södra speciellt mellan 2010 och 2015, medan elförbrukningen skulle vara stabil under hela perioden i området Stockholm Norra. Det finns en risk för att under ett antal timmar vid riktigt kall vinter, ha ett elbehov högre än Vattenfall Eldistributions summa av abonnemang. Dock är det väldigt låg sannolikhet att detta händer, vilket innebär att det förmodligen finns andra sätt att hantera denna efterfråga på el än att öka överföringskapaciteten i elnätet. Examensarbetet resulterar i flera frågor. Exempelvis att utreda möjligheter i att utnyttja lokala el och värmekraftverk och använda elprissignaler. Ytterligare arbete kan också undersöka scenarier av den framtida elförbrukning i en mindre skala.