Grandes saltos tecnológicos viabilizaram a integração de circuitos digitais de alta complexidade, com centenas de pinos e milhões de transistores. Sistematicamente, dispositivos eletromecânicos estão sendo substituídos por Circuitos Integrados (CIs) que contêm sistemas inteiros, ampliando o uso generalizada da eletrônica. Com o aumento da complexidade e quantidade de CIs produzidos, a tarefa de detectar de forma rápida e eficiente aqueles chips com problemas assumiu grande importância. Como a Testabilidade [McClu 86] de um CI afeta sua qualidade, um circuito que não é completamente testável, para um determinado modelo de falha, tem menos valor que outro inteiramente testável [De Mi 94]. Em estudos sobre confiabilidade, desempenho, custos e Testabilidade de circuitos VLSI verificou-se que o custo associado ao processo de testes de circuitos VLSI estava praticamente estabilizado, enquanto outros componentes do preço final do chip caíam. Por estas razões, a Testabilidade foi incorporada ao projeto desde suas concepções iniciais, apresentando geralmente resultados com menor Sobreárea e mínimo impacto no desempenho, quando comparado a CIs produzidos sem considerações relacionadas a testes. Uma técnica de teste que dispensa o uso de Equipamento Automático de Teste, conhecida como Autoteste Incorporado (em inglês, Built-In Self-Test – BIST), consiste em adaptar partes do próprio CI para gerar Vetores de Teste, comprimir e analisar os resultados. A técnica BIST tem sido empregada com sucesso em ambientes de projeto de Síntese de Alto Nível (High Level Synthesis, HLS), que tende a reduzir o tempo de projeto de um ASIC, auxiliando a determinação da arquitetura RTL [Stru et al. 99]. Nesta dissertação, considera-se uma forma específica de BIST, o structural off-line BIST [Abr et al. 90], em que o Autoteste se dá quando o CI digital é retirado de sua operação normal e colocado em modo teste, para que um Plano de Teste para Unidades Funcionais seja executado (na fase de manufatura e/ou de serviço em campo). O Plano de Teste, baseado em uma descrição estrutural do CI, é gerado por um algoritmo concebido para detectar os registradores que devem ser reconfigurados em Geradores de Padrões de Teste (em inglês, Test Pattern Generators, TPGs) e Analisadores de Assinatura (Signature Analyzers, SAs). O critério de seleção dos registradores baseia-se numa Função Custo, que avalia globalmente o grau de compartilhamento de cada registrador candidato, e a contribuição que a sua eventual escolha causaria no tempo final de teste. Os Registradores de Teste, reconfigurados em Autômatos Celulares (Cellular Automata, CAs), devem operar segundo um “Rule Number", neste caso, Regra 90 ou 150. A tarefa do Autoteste paralelo é dividida em duas etapas: na primeira, a cada uma das Unidades Funcionais é associado o melhor momento possível para início de sua sessão de teste, resultando na construção gradativa de uma Matriz de Estado de Teste, e na segunda, com a Matriz de Estado de Teste já totalmente definida, é feita uma análise global para minimizar o número de candidatos a registrador de teste. O resultado final é um Plano de Teste Otimizado definindo as regras dos TPGs (TPG90 e/ou TPG150), o custo em termos de Sobreárea, o início da geração dos Vetores de Teste, sua duração e a Cobertura de Falha mínima. / Great technological developments have made possible the integration of digital circuits of high complexity, with hundreds of pins and million of transistors. Electromechanical devices are being systematically substituted for Integrated Circuits (ICs) that contain complete systems, extending the generalized use of electronics. With the increasing complexity and amount of ICs, the task of detecting faulty chips in a fast and efficient way has assumed great importance. As testability [McClu 86] affects the quality of an IC, a circuit that is not fully testable for one determined fault model has less value than another which is entirely testable [De Mi 94]. It was verified in studies on reliability, performance, costs and testability of VLSI circuits that the cost associated with tests was practically stabilized, while other components of the final price fell. For these reasons, testability was incorporated in the design since its initial conception, producing generally minor area overhead and minimum impact on the performance, when compared to ICs produced without test considerations. One test technique that eliminates de needs for use of Automatic Test Equipment, known as BIST - Built-In Self-Test, consists of adapting parts of the IC to generate Test Vectors, compress and analyze the results. The BIST technique has been used successfully in design of HLS - High Level Synthesis - environments, which tends to reduce the ASIC’s design time, easing the task of determining the RTL architecture [Stru et al. 99]. In this dissertation a specific form of BIST, the structural off-line BIST [Abr et al. 90], is considered. To start the self-test it is necessary to halt the normal operation of the digital IC and put it in test mode, so that a Test Plan for Functional Units is executed (in the phase of manufacture and/or in the field). The Test Plan based on the structure of the IC is generated by an algorithm conceived to detect the registers which will be reconfigured in TPGs - Test Pattern Generators, and SAs - Signature Analyzers. The criterion for selection of the registers is based on a Cost Function, which globally evaluates the degree of sharing of each register candidate, and the contribution that its eventual choice would cause in the final test time. The Test Registers reconfigured in CAs – Cellular Automata - must operate according to a “Rule Number", in this case Rule 90 or 150. The task of the parallel self-test is divided into two stages: in the first one, to each Functional Unit is associated the best possible moment for its test session beginning, resulting in the gradual construction of a Test Status Matrix, and in the second, with the Test Status Matrix completely defined, a global analysis is made to minimize the number of register candidates. The final result is an Optimized Test Plan, which defines the rules of the TPGs (TPG90 and/or TPG150), the area overhead cost, the beginning of the Test Vector Generation, its duration and the minimum Fault Coverage.

Le secteur du chauffage, de la ventilation et de la climatisation (Heating Ventilation and Air-Conditioning,HVAC) se doit, comme toute industrie d’envergure, de maîtriser la fiabilité de ses produits pour garantir un service optimal au client, réduire les délais de développement et maîtriser ses coûts. Pour ce faire, il est indispensable de connaitre et savoir appliquer les outils de fiabilité prévisionnelle, expérimentale et opérationnelle. Seule une méthodologie robuste permettant de définir une stratégie de qualification permet de garantir la tenue de l’objectif de fiabilité.La première partie de ce travail définit les problématiques ayant attrait à la fiabilité et fait l’inventaire des méthodes existantes dans des domaines connexes et surtout dans le domaine HVAC.Dans un second temps la méthodologie de qualification est proposée, avec un focus sur l’exploitation du retour d’expérience, la définition des objectifs de fiabilité et tous les plans d’essais possibles. Enfin, des exemples concrets mis en place chez CIAT (UTC) sont détaillées dans une dernière partie. / The heating, ventilation and air conditioning (HVAC) field, as any other large industry, must control the reliability of its products in order to guarantee an optimal service to customers, reduce development limits and master its costs. To achieve it, predicted, experimental and operational reliability tools should be known and well applied. Only a strong methodology leading to a qualification strategy can ensure the holding of the reliability target. The first part of this work defines reliability terms and inventories existing methods in related fields and specifically in HVAC. Following that, the qualification methodology is detailed, focusing on feedback, definition of reliability targets and possible test plans. Finally, specific examples implemented at CIAT (UTC) are detailed in final part.

Grandes saltos tecnológicos viabilizaram a integração de circuitos digitais de alta complexidade, com centenas de pinos e milhões de transistores. Sistematicamente, dispositivos eletromecânicos estão sendo substituídos por Circuitos Integrados (CIs) que contêm sistemas inteiros, ampliando o uso generalizada da eletrônica. Com o aumento da complexidade e quantidade de CIs produzidos, a tarefa de detectar de forma rápida e eficiente aqueles chips com problemas assumiu grande importância. Como a Testabilidade [McClu 86] de um CI afeta sua qualidade, um circuito que não é completamente testável, para um determinado modelo de falha, tem menos valor que outro inteiramente testável [De Mi 94]. Em estudos sobre confiabilidade, desempenho, custos e Testabilidade de circuitos VLSI verificou-se que o custo associado ao processo de testes de circuitos VLSI estava praticamente estabilizado, enquanto outros componentes do preço final do chip caíam. Por estas razões, a Testabilidade foi incorporada ao projeto desde suas concepções iniciais, apresentando geralmente resultados com menor Sobreárea e mínimo impacto no desempenho, quando comparado a CIs produzidos sem considerações relacionadas a testes. Uma técnica de teste que dispensa o uso de Equipamento Automático de Teste, conhecida como Autoteste Incorporado (em inglês, Built-In Self-Test – BIST), consiste em adaptar partes do próprio CI para gerar Vetores de Teste, comprimir e analisar os resultados. A técnica BIST tem sido empregada com sucesso em ambientes de projeto de Síntese de Alto Nível (High Level Synthesis, HLS), que tende a reduzir o tempo de projeto de um ASIC, auxiliando a determinação da arquitetura RTL [Stru et al. 99]. Nesta dissertação, considera-se uma forma específica de BIST, o structural off-line BIST [Abr et al. 90], em que o Autoteste se dá quando o CI digital é retirado de sua operação normal e colocado em modo teste, para que um Plano de Teste para Unidades Funcionais seja executado (na fase de manufatura e/ou de serviço em campo). O Plano de Teste, baseado em uma descrição estrutural do CI, é gerado por um algoritmo concebido para detectar os registradores que devem ser reconfigurados em Geradores de Padrões de Teste (em inglês, Test Pattern Generators, TPGs) e Analisadores de Assinatura (Signature Analyzers, SAs). O critério de seleção dos registradores baseia-se numa Função Custo, que avalia globalmente o grau de compartilhamento de cada registrador candidato, e a contribuição que a sua eventual escolha causaria no tempo final de teste. Os Registradores de Teste, reconfigurados em Autômatos Celulares (Cellular Automata, CAs), devem operar segundo um “Rule Number”, neste caso, Regra 90 ou 150. A tarefa do Autoteste paralelo é dividida em duas etapas: na primeira, a cada uma das Unidades Funcionais é associado o melhor momento possível para início de sua sessão de teste, resultando na construção gradativa de uma Matriz de Estado de Teste, e na segunda, com a Matriz de Estado de Teste já totalmente definida, é feita uma análise global para minimizar o número de candidatos a registrador de teste. O resultado final é um Plano de Teste Otimizado definindo as regras dos TPGs (TPG90 e/ou TPG150), o custo em termos de Sobreárea, o início da geração dos Vetores de Teste, sua duração e a Cobertura de Falha mínima. / Great technological developments have made possible the integration of digital circuits of high complexity, with hundreds of pins and million of transistors. Electromechanical devices are being systematically substituted for Integrated Circuits (ICs) that contain complete systems, extending the generalized use of electronics. With the increasing complexity and amount of ICs, the task of detecting faulty chips in a fast and efficient way has assumed great importance. As testability [McClu 86] affects the quality of an IC, a circuit that is not fully testable for one determined fault model has less value than another which is entirely testable [De Mi 94]. It was verified in studies on reliability, performance, costs and testability of VLSI circuits that the cost associated with tests was practically stabilized, while other components of the final price fell. For these reasons, testability was incorporated in the design since its initial conception, producing generally minor area overhead and minimum impact on the performance, when compared to ICs produced without test considerations. One test technique that eliminates de needs for use of Automatic Test Equipment, known as BIST - Built-In Self-Test, consists of adapting parts of the IC to generate Test Vectors, compress and analyze the results. The BIST technique has been used successfully in design of HLS - High Level Synthesis - environments, which tends to reduce the ASIC’s design time, easing the task of determining the RTL architecture [Stru et al. 99]. In this dissertation a specific form of BIST, the structural off-line BIST [Abr et al. 90], is considered. To start the self-test it is necessary to halt the normal operation of the digital IC and put it in test mode, so that a Test Plan for Functional Units is executed (in the phase of manufacture and/or in the field). The Test Plan based on the structure of the IC is generated by an algorithm conceived to detect the registers which will be reconfigured in TPGs - Test Pattern Generators, and SAs - Signature Analyzers. The criterion for selection of the registers is based on a Cost Function, which globally evaluates the degree of sharing of each register candidate, and the contribution that its eventual choice would cause in the final test time. The Test Registers reconfigured in CAs – Cellular Automata - must operate according to a “Rule Number”, in this case Rule 90 or 150. The task of the parallel self-test is divided into two stages: in the first one, to each Functional Unit is associated the best possible moment for its test session beginning, resulting in the gradual construction of a Test Status Matrix, and in the second, with the Test Status Matrix completely defined, a global analysis is made to minimize the number of register candidates. The final result is an Optimized Test Plan, which defines the rules of the TPGs (TPG90 and/or TPG150), the area overhead cost, the beginning of the Test Vector Generation, its duration and the minimum Fault Coverage.

Robotics and Automation field is booming in today´s scenario. Researchers and Technologist comes up with new ideas in the robotics field to achieve a higher productivity, flexibility and efficiency. To achieve the above goals, it shall be required that human and robot share their work space with each other and works in a collaborative nature. Safety is a main concern and in focus. Robot should not injure the operator in any way during working in robotic cell. In this master thesis main focus is to create a various test plans and validate them to ensure the safety level in robotic cell. The test plan should be validated in a real robot environment. The test plans consist of functional and individual verification of safety devices which are being used in a robotic cell at PTC which is known as smart automation lab. Apart from that it includes design simulation of robotic cells with manikins to ensure validation of safety in virtual environment. Design simulation of robotic cell with manikins are created in RobotStudio 6.06. However, smart components, trap routines, SafeMove and offline program in RAPID have been created. Various test results are incorporated in the results section to ensure the verification and validation of safe human robot collaboration of virtual environment in RobotStudio 6.06.

The diploma thesis deals with the solution of selected parts of the the construction technology project of the town covered swimming pool in Luhačovice. The project includes engineering report, design site equipment and crane, technological instruction for drilled pile and piled wall, supervisory and test plans. For the substructure deals with building noise and noise protection. Next it deals with the itemized budget of the gross building and detailed time plan.

The aim of this diploma´s thesis is the construction and technological salutions to rough construction building municipal sports hall in Kuřim. The content of this work is technological execution, solution to site equipment, design of machanical assemblies sonnected with transport links, checking and test plans, line budget, schedule, calculation of construction, building timetable, safety and protection of enviroment.

The diploma thesis deals with construction and technological solution of Hotel Sachrův kopec in Harrachov. Part of the thesis is technical report of main object, study of realization main technological phases, technological prescriptions and inspection and test plans for steel-concrete ceiling construction, copper roof cover and Spiroll panel ceiling construction. Thesis contain project of work side facilities, main construction machinery, shedule of health and safety, environmental protection, coordination situation of transport routes, time and financial plan for construction, drawing of formwork for steel-concrete ceiling construction and drawing of Spiroll panel ceiling.

This Thesis deals with the organization of realization of the residential building A1 Slavkov u Brna. Thesis solves mainly technological process of realization of the main object. The thesis aims to develop a time schedule of execution, usage of mechanisms timetable, material resources, technological regulations, inspection and test plans. The annex also solved graphically construction site facility set up and its modifications during execution depending on different type of works. This Thesis is based on realization project provided by the realization company and with consent of project designer.

This diploma thesis addresses the „University Campus Bohunice - Architectural and technological project“. This thesis includes excavation, pile foundation, reinforced concrete foundation slab it also deals with in detail technological regulations on earthworks and deep-pile foundation. The thesis contains solutions to building equipment, schedule of selected stages of the construction situation with the solution of transport routes, designed mechanical assembly required for selected stages and control plan earthworks and deep-pile foundation. This diploma thesis addresses the „University Campus Bohunice - Architectural and technological project“. This project involves construction of two buildings. Building A32 with two basement floors and three floors and second building A 31 with one basement floor and three floors. This thesis includes excavation, pile foundation, reinforced concrete foundation slab, it also deals with technological regulations of earthworks and deep-pile foundation in detail. The thesis contains solutions to construction site equipment, schedule of selected stages of the construction, location of buildings and the solution of transport routes, mechanical equipment required for selected stages of project and control plan of earthworks and deep-pile foundation.

This diplome thesis is focused on the technological project of the gross building of the Laboratory Center UTB in Zlín. Among other subjects, the work consists of technical report, technical rule, inspection and test plans, mechanical assembly desing, financial comparison of various casting methods, health and safety plan, environmental protection issues, budget, timetable and building site situation.