No description available.

"none"

No description available.

Based on .Net Framework4.0 development platform and Visual C# language, this thesis presents various methods of performing lane detection and preceding vehicle detection/tracking with code optimization and acceleration to reduce the execution time. The thesis consists of two major parts: vehicle detection and tracking. In the part of detection, driving lanes are identified first and then the preceding vehicles between the left lane and right lane are detected using the shadow information beneath vehicles. In vehicle tracking, three-pass search method is used to find the matched vehicles based on the detection results in the previous frames. According to our experiments, the preprocessing (including color-intensity conversion) takes a significant portion of total execution time. We propose different methods to optimize the code and speed up the software execution using pure C # pointers, OPENCV, and OPENCL etc. Experimental results show that the fastest detection/tracking speed can reach more than 30 frames per second (fps) using PC with i7-2600 3.4Ghz CPU. Except for OPENCV with execution rate of 18 fps, the rest of methods have up to 28 fps processing rate of almost the real-time speed. We also add the auxiliary vehicle information, such as preceding vehicle distance and vehicle offset warning.

The electronics newspaper becomes a main source for online news readers. When facing the numerous stories, news readers need some supports in order to review a topic in short time. Due to previous researches in TDT (Topic Detection and Tracking) only considering how to identify events and present the results with news titles and keywords, a summarized text to present event evolution is necessary for general news readers to retrospect events under a news topic. This thesis proposes a topic retrospection process and implements the SToRe system that identifies various events under a new topic and constructs the relationship to compose a summary which gives readers the sketch of event evolution in a topic. It consists of three main functions: event identification, main storyline construction and storyline-based summarization. The constructed main storyline can remove the irrelevant events and present a main theme. The summarization extracts the representative sentences and takes the main theme as the template to compose summary. The summarization not only provides enough information to comprehend the development of a topic, but also can be an index to help readers to find more detailed information. A lab experiment is conducted to evaluate the SToRe system in the question-and-answer (Q&A) setting. From the experimental results, the SToRe system can help news readers more effectively and efficiently to capture the development of a topic.

Modern computer systems are power or energy limited. While the number of transistors per chip continues to increase, classic Dennard voltage scaling has come to an end. Therefore, architects must improve a design's energy efficiency to continue to increase performance at historical rates, while staying within a system's power limit. Throughput processors, which use a large number of threads to tolerate memory latency, have emerged as an energy-efficient platform for achieving high performance on diverse workloads and are found in systems ranging from cell phones to supercomputers. This work focuses on graphics processing units (GPUs), which contain thousands of threads per chip. In this dissertation, I redesign the on-chip storage system of a modern GPU to improve energy efficiency. Modern GPUs contain very large register files that consume between 15%-20% of the processor's dynamic energy. Most values written into the register file are only read a single time, often within a few instructions of being produced. To optimize for these patterns, we explore various designs for register file hierarchies. We study both a hardware-managed register file cache and a software-managed operand register file. We evaluate the energy tradeoffs in varying the number of levels and the capacity of each level in the hierarchy. Our most efficient design reduces register file energy by 54%. Beyond the register file, GPUs also contain on-chip scratchpad memories and caches. Traditional systems have a fixed partitioning between these three structures. Applications have diverse requirements and often a single resource is most critical to performance. We propose to unify the register file, primary data cache, and scratchpad memory into a single structure that is dynamically partitioned on a per-kernel basis to match the application's needs. The techniques proposed in this dissertation improve the utilization of on-chip memory, a scarce resource for systems with a large number of hardware threads. Making more efficient use of on-chip memory both improves performance and reduces energy. Future efficient systems will be achieved by the combination of several such techniques which improve energy efficiency. / text

Chemistry / Although molecules that bind DNA have the potential to modify gene expression, the reality of targeting DNA in a sequence-specific manner is still a problematic but worthwhile goal. The Iverson lab has been exploring DNA recognition through a motif known as threading polyintercalation based on connecting intercalating naphthalene diimide (NDI) units, which are molecules that insert themselves between DNA base pairs, together with peptide linkers. These polyintercalators interact with both DNA grooves by “threading” or winding through the DNA, like a snake might climb a ladder. Initially, two different bisintercalator modules with altered sequence specificities and different groove binding topologies were discovered and used to inspire the design of a hybrid NDI tetraintercalator. Surprisingly enough, this tetraintercalator bound sequence-specifically with a dissociation half-life of 16 days to its preferred 14 bp site, a record at the time it was reported for a synthetic DNA-binding molecule. The work reported here expands on the capabilities of this modular threading polyintercalation motif. Chapter 2 describes the ability of a new hybrid NDI tetraintercalator, where the bisintercalator modules are connected together in a different way compared to the previously studied tetraintercalator, to subtly discriminate between similar binding sites. Chapter 3 offers a structural understanding, through NMR analysis, for the sequence recognition abilities of this new tetraintercalator. Chapter 4 analyzes the binding abilities of an un-optimized NDI octaintercalator and proposes how to approach the second-generation design of longer polyintercalators. Chapter 5 describes the optimization of the originally designed NDI tetraintercalator by serially lengthening one of the linkers to produce a tetraintercalator with a 57 day dissociation half-life from its 14 bp sequence, a new record for a synthetic DNA-binding molecule. Using the optimized linker in the context of an NDI hexaintercalator allows for binding to a 22 bp designed site, a record for a synthetic non-nucleic acid molecule. Chapter 6 recounts a focused library screening to search for bisintercalators with new sequence specificities. These efforts have laid the groundwork to progress toward studies aimed at understanding how these molecules might function to prevent transcription in a sequence-dependent manner in vivo. / text

This work gives the overview of particularities of parallel programming for the personal computer and the observation of the possibilities and advantages of the Hyper-Threading technology and new Pentium 4 processors. The work proves that the creation of the Hyper-Threading technology and dual-core processors helps to make parallel computing more available for the usual personal computer. Parallel programming becomes not only the way of solving difficult tasks but gives a real possibility to speed up the work of personal computer and to use its hardware resources more effectively. The work gives the review of the possibilities of creation of parallel programs by using OpenMP standard and particularities of the application of the set of SSE2 processor commands. The results of practical tests are given. They indicate that the floating point computing is more effective without using of multiple threads and Hyper-Treading technology shows best results working with different types of processes or working with new processor possibilities.

In multi-view video applications, view synthesis is a computationally intensive task that needs to be done correctly and efficiently in order to deliver a seamless user experience. In order to provide fast and efficient view synthesis, in this thesis, we present a cloud-based implementation that will be especially beneficial to mobile users whose devices may not be powerful enough for high quality view synthesis. Our proposed implementation balances the view synthesis algorithm’s components across multiple threads and utilizes the computational capacity of modern CPUs for faster and higher quality view synthesis. For arbitrary view generation, we utilize the depth map of the scene from the cameras’ viewpoint and estimate the depth information conceived from the virtual camera. The estimated depth is then used in a backward direction to warp the cameras’ image onto the virtual view. Finally, we use a depth-aided inpainting strategy for the rendering step to reduce the effect of disocclusion regions (holes) and to paint the missing pixels. For our cloud implementation, we employed an automatic scaling feature to offer elasticity in order to adapt the service load according to the fluctuating user demands. Our performance results using 4 multi-view videos over 2 different scenarios show that our proposed system achieves average improvement of 3x speedup, 87% efficiency, and 90% CPU utilization for the parallelizable parts of the algorithm.

Background - Web browsers and and the web programs on them are being used now more than ever in a manner similar to traditional software. But with the increase in the demand for performance on bigger and bigger web applications, there is a need for making the web applications perform faster and better. Introducing parallelism to a normally single threaded system is one popular way of introducing more performance. Objectives - We will implement proven and workable programs, created with OpenMP, that will be translated to JavaScript. These JavaScript applications will use the WebWorkers API to achieve similar levels of parallelism as the OpenMP applications. Methods - To implement and gather results from the all of the various programs, we will be using visual studio code and its live server extension that it hosts to run and compare the JavaScript implementations. The selected OpenMP applications to be measured and translated were primarily taken and selected from a benchmark suite that hosts programs that have already been written in a traditional parallel computing model, such as OpenMP. The performance of these OpenMP programs and Web Workers applications will be analyzed and compared in the second portion of the research where results will be gathered. Results - JavaScript was proven to perform worse than OpenMP in every situation tested. Though this was expected, there were also some situations where JavaScript applications were performing close to the OpenMP programs. Conclusions - Ultimately, using Web Workers is recommended for what they were designed to do. To help alleviate the main thread to keep the web program running smoothly. For the heavy computational tasks that we were experimenting on, JavaScript did not do a sufficient enough job compared against the OpenMP applications. When measuring the workers we did not get any results for any applicationsthat was very close to what OpenMP achieved. Thus Web Workers are really only suited for easy problems that needs to be done repeatedly. They lack the efficiency for any complicated algorithms to be worth implementing