<p dir="ltr">The proliferation of internet-connected embedded devices in contemporary computing environments has raised significant concerns regarding data security and confidentiality. Most embedded devices rely on computationally secure cryptographic algorithms to address these imperatives. However, despite the mathematical assurances, the physical implementation of these algorithms introduces vulnerabilities. Specifically, side-channel analysis (SCA) attacks exploit information leakage through various channels, including power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, and other observable characteristics. </p><p dir="ltr">Previous research has introduced the concept of attenuating information-sensitive signatures using an analog cascoded current source for power delivery, coupled with an analog biased PMOS-based local negative feedback mechanism to stabilize the internal node. While this approach achieves robust signature suppression, resulting in higher minimum traces to disclosure (MTD) and enhanced security, it remains limited by its analog nature, making it less adaptable across different technology nodes. This thesis proposes a digital-friendly signature suppression technique that employs a digital cascoded current source and leverages a Ring-oscillator-based bleed path. These digital countermeasures can be further enhanced through time-domain obfuscation techniques. Our work demonstrates a state-of-the-art MTD of 1.25 billion traces for an AES-256 implementation. However, these countermeasures lack provable security guarantees, so continuous stress testing is essential for widespread deployment. Different intelligent attacks can be exploited on these physical countermeasures. Notably, this thesis also presents an intelligent attack on signature attenuation-based physical countermeasures and introduces an attack detector. Developing an intelligent attack detector is an integral part of the commercial adoption of physical countermeasures. </p><p dir="ltr">Next, generic physical countermeasures are often deployed in the $V_{DD}$ port as power side channel analysis is carried out through the $V_{DD}$ port. However, any digital circuit has two standard ports, namely $V_{DD}$ and clock port, and countermeasure through the clock port is mainly unexplored except for the system-level clock randomization technique. Even the clock-randomization technique is rendered ineffective in the presence of post-processing techniques. This thesis introduces a side channel resilience technique by introducing a larger slew at the clock, thereby improving MTD by $100\times$.</p><p dir="ltr">Next, these physical countermeasures do not come with any provable security guarantee. Hence, it is important to stress-test the countermeasures. This thesis does so and finds an exploitable point to reduce MTD by 1000$\times$. An attack detector of such an attack is also proposed.</p><p dir="ltr">Further, an attack detection strategy against side-channel analysis (SCA) or fault injection attacks (FIA) is also required. A detection and mitigation approach often gives us the option of duty-cycled countermeasures, hence reducing the energy overhead. This thesis proposes and analyzes a self-aware inductive loop-based attack detection strategy to detect SCA and FIA and enhance the signature attenuation countermeasures. </p><p dir="ltr">Finally, we explore opportunities for integrating these lightweight generic techniques into recently standardized Post-Quantum Cryptographic (PQC) cores. Specifically, we present an optimized implementation of the Saber PQC core, a NIST standardization finalist, achieving the lowest area and energy consumption. Future work could involve deploying lightweight PQC cores with synthesizable physical countermeasures to enhance security against quantum algorithms and physical side-channel attacks.</p>