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Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuitsLynch, John Daniel 10 1900 (has links)
Ph.D. / Electrical Engineering / The expected unreliability of nano-scale electronic components has renewed interest in the decades-old field of fault-tolerant logic design. Fault-tolerant design makes it possible to build reliable systems from unreliable components. This has spurred recent research into the application of classical FT techniques to nanoelectronics. Meanwhile, the growing gap between logic gate and wire delays, and the growing power consumption of clock generation and distribution circuits, in nanometer-scale silicon integrated circuits has renewed research in asynchronous, or clockless, logic design. This dissertation examines the application of triple modular redundancy (TMR), one of several FT circuit design techniques, to improve the reliability of a variety of clockless circuits and systems. A new fault model, appropriate for clockless circuits is derived and applied to measure the reliability of nonredundant and triplex micropipelines. A new circuit element that combines the functionality of a Muller C-element and a majority gate is introduced to solve special problems at the simplex-triplex interface. The effectiveness of asynchronous FT circuit design strategies based on the results of Monte Carlo simulation experiments with representative circuits modeled in Verilog hardware description language (HDL) is presented.
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Design and analysis of robust algorithms for fault tolerant computingJang, Jai Eun 04 April 1990 (has links)
Graduation date: 1990
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Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancyChang, Sanghoan 15 May 2009 (has links)
The operating clock frequency is determined by the longest signal propagation
delay, setup/hold time, and timing margin. These are becoming less predictable with
the increasing design complexity and process miniaturization. The difficult challenge
is then to ensure that a device operating at its clock frequency is error-free with
quantifiable assurance. Effort at device-level engineering will not suffice for these
circuits exhibiting wide process variation and heightened sensitivities to operating
condition stress. Logic-level redress of this issue is a necessity and we propose a
design-level remedy for this timing-uncertainty problem.
The aim of the design and analysis approaches presented in this dissertation is to
provide framework, SABRE, wherein an increased operating clock frequency can be
achieved. The approach is a combination of analytical modeling, experimental analy-
sis, hardware /time-redundancy design, exception handling and recovery techniques.
Our proposed design replicates only a necessary part of the original circuit to avoid
high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical
combinational circuit is path-wise partitioned into two sections. The combinational
circuits associated with long paths are laid out without any intrusion except for the
fan-out connections from the first section of the circuit to a replicated second section
of the combinational circuit. Thus only the second section of the circuit is replicated.
The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed
at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the
likelihood of mistiming due to stress or process variation is eliminated. During the
subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved,
circuit outputs are compared to detect faults. When a fault is detected, the retry sig-
nal is triggered and the dynamic frequency-step-down takes place before a pipe flush,
and retry is issued. The significant timing overhead associated with the retry is offset
by the rarity of the timing violation events. Simulation results on ISCAS Benchmark
circuits show that 10% of clock frequency gain is possible with 10 to 20 % of hardware
overhead of replicated timing-critical circuit.
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Comparison of numerical result checking mechanisms for FFT computations under faultsBharthipudi, Saraswati. January 2003 (has links) (PDF)
Thesis (M.S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Dr. Feodor Vainstein, Committee Member; Dr. Doug Blough, Committee Chair; Dr. David Schimmel, Committee Member. Includes bibliographical references (leaves 71-75).
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VLSI implementation of cross-parity and modified dice fault tolerant schemesBlum, Daniel Ryan, January 2004 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Washington State University. / Includes bibliographical references.
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Root growth dynamics and cultivation aspects of Kosteletzkya virginica (Malvaceae)Halchak, Jennifer L. January 2009 (has links)
Thesis (M.S.)--University of Delaware, 2009. / Principal faculty advisor: John L. Gallagher, College of Earth, Ocean, & Environment. Includes bibliographical references.
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Fault-tolerant wormhole routing for mesh computersZhou, Jipeng. January 2001 (has links)
Thesis (Ph. D.)--University of Hong Kong, 2001. / Includes bibliographical references (leaves 114-120).
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Measures of inexact diagnosabilityCrick, David Alan 12 1900 (has links)
No description available.
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Investigation of precision versus fault tolerance in voting algorithmsParameswaran, Rupa 12 1900 (has links)
No description available.
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Design and analysis of fault-tolerant pipelined multicomputer networksGaughan, Patrick T. 05 1900 (has links)
No description available.
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