Thesis (Ph. D.)--State University of New York at Binghamton, Department of Electrical Engineering and Computer Engineering, 2006. / Includes bibliographical references (leaves 107-122).

Thesis (M.S.)--Worcester Polytechnic Institute. / Keywords: intrusion detection system; Byzantine Agreement Protocol. Includes bibliographical references (p. 43-44).

Thesis (M. Phil.)--University of Hong Kong, 1997. / Includes bibliographical references (leaves 111-112).

Thesis (M.S. in botany)--Washington State University, August 2009. / Title from PDF title page (viewed on Sept. 22, 2009). "Department of Biological Sciences." Includes bibliographical references (p. 138-139).

Thesis (Ph. D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2004. / "A dissertation in computer networking and telecommunication networking." Advisor: Deep Medhi. Typescript. Vita. Title from "catalog record" of the print edition Description based on contents viewed Feb. 24, 2006. Includes bibliographical references (leaves 140-147). Online version of the print edition.

Thesis (M.S. in electrical engineering)--Washington State University, August 2007. / Includes bibliographical references (p. 57-59).

No description available.

Embedded systems which are targeted towards portable applications are required to have low power consumption because such portable devices are typically powered by batteries. During the memory accesses of such battery operated portable systems, including laptops, cell phones and other devices, a significant amount of power or energy is consumed which significantly affects the battery life. Therefore, efficient and leakage power saving cache designs are needed for longer operation of battery powered applications. Design engineers have limited control over many design parameters of the circuit and hence face many chal-lenges due to inherent process technology variations, particularly on static random access memory (SRAM) circuit design. As CMOS process technologies scale down deeper into the nanometer regime, the push for high performance and reliable systems becomes even more challenging. As a result, developing low-power designs while maintaining better performance of the circuit becomes a very difficult task. Furthermore, a major need for accurate analysis and optimization of various forms of total power dissipation and performance in nanoscale CMOS technologies, particularly in SRAMs, is another critical issue to be considered. This dissertation proposes power-leakage and static noise margin (SNM) analysis and methodologies to achieve optimized static random access memories (SRAMs). Alternate topologies of SRAMs, mainly a 7-transistor SRAM, are taken as a case study throughout this dissertation. The optimized cache designs are process-voltage-temperature (PVT) tolerant and consider individual cells as well as memory arrays.

Spores from a weakly salt tolerant strain of Ceratopteris richardii containing the mutation stl1 were irradiated and sown on nutrient medium supplemented with 200 m M NaCl. A single highly salt tolerant gametophyte was recovered and selfed to generate a homozygous sporophyte. Spores from this strain, 10α23, were used to document the sexual transmission of the trait and to monitor the inheritance of tolerance in crosses to both the wild type and to the parental salt tolerant strain. Genetic analysis showed the 10α23 strain to possess both the original stl1 mutation and an additional semi-dominant nuclear mutation, stl2, that individually conferred a high level of tolerance to gametophytes. In combination, both mutations had additive effects. Tolerance was also evident in sporophytes, but at a lower level than in gametophytes.

No description available.