Field Programmable Gate Arrays (FPGAs) are reconfigurable, high-performing devices that are often used in critical applications. However, like all semiconductors, FPGAs experience transistor aging that can lower performance and lead to device failures. Additionally, device aging also has several security implications. Therefore, understanding the aging mechanisms behind transistor aging is necessary to ensure the reliability of FPGAs. However, current aging studies either rely on simulation alone or are unable to isolate aging effects on specific elements within the FPGA. This dissertation uses the reconfigurability of FPGAs to develop novel aging techniques that allow for the targeted aging of specific areas of the FPGA fabric. This allows us to manipulate the performance variation of a device, which allows for several interesting security applications. In addition, we use precise characterization methods that, when combined with our fine-grained aging techniques, allow us to isolate the effects of aging on individual paths and elements within the FPGA. This provides valuable insights into FPGA aging which can be used to develop new aging mitigation strategies. This dissertation is comprised of five major contributions. The first contribution uses thousands of short circuits to induce a non-uniform slowdown of an FPGA's programmable fabric. The second contribution demonstrates how modifier circuits can be inserted into a region of short circuits to perform more precise aging to a targeted region and allow us to manipulate performance variation at the tile level of an FPGA. The third contribution uses our targeted aging technique to demonstrate two security applications: frequency watermark and cloning a ring oscillator physical unclonable function (RO PUF) on an FPGA. The fourth contribution uses carefully crafted stress circuits and precise characterization methods to isolate the effects of transistor aging on individual paths within the FPGA. The final contribution uses elements of our precise characterization techniques to create a more reliable configurable RO PUF (CRO PUF) for cryptographic key generation on FPGAs.