The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases. A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals. A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Oct. 1, 2012 - Oct. 1, 2014

Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply.

Field Programmable Gate Arrays (FPGAs) are reconfigurable, high-performing devices that are often used in critical applications. However, like all semiconductors, FPGAs experience transistor aging that can lower performance and lead to device failures. Additionally, device aging also has several security implications. Therefore, understanding the aging mechanisms behind transistor aging is necessary to ensure the reliability of FPGAs. However, current aging studies either rely on simulation alone or are unable to isolate aging effects on specific elements within the FPGA. This dissertation uses the reconfigurability of FPGAs to develop novel aging techniques that allow for the targeted aging of specific areas of the FPGA fabric. This allows us to manipulate the performance variation of a device, which allows for several interesting security applications. In addition, we use precise characterization methods that, when combined with our fine-grained aging techniques, allow us to isolate the effects of aging on individual paths and elements within the FPGA. This provides valuable insights into FPGA aging which can be used to develop new aging mitigation strategies. This dissertation is comprised of five major contributions. The first contribution uses thousands of short circuits to induce a non-uniform slowdown of an FPGA's programmable fabric. The second contribution demonstrates how modifier circuits can be inserted into a region of short circuits to perform more precise aging to a targeted region and allow us to manipulate performance variation at the tile level of an FPGA. The third contribution uses our targeted aging technique to demonstrate two security applications: frequency watermark and cloning a ring oscillator physical unclonable function (RO PUF) on an FPGA. The fourth contribution uses carefully crafted stress circuits and precise characterization methods to isolate the effects of transistor aging on individual paths within the FPGA. The final contribution uses elements of our precise characterization techniques to create a more reliable configurable RO PUF (CRO PUF) for cryptographic key generation on FPGAs.

The temperature sensor design discussed in this thesis, is meant mainly to monitor temperature at power outlets. Current variations in power cords have a direct impact on the surrounding temperature. Sensing these variations ,enables us to take necessary measures to prevent any hazards due to temperature rise. Thus, for this application we require a sensor with a moderate temperature error (_10C) over a sensing range of -200C to 1500C. Low power consumption and simple digitizing scheme alleviate measurement errors due to self heating effects of the sensor. A current starved inverter based ring oscillator was chosen for the sensor design in 130nm technology. The inverter delay variation with temperature is used for sensing. Linearity and process invariancy of these characteristics are fundamental to the sensor design. We observed through simulations, and confirmed by mathematical analysis, that the sensing characteristics are governed by bias current dependence on temperature. Control voltage for the bias circuitry of the oscillator determines current through the inverter stages. Hence, for linear sensing characteristics, a control voltage(Vc) just above the maximum threshold voltage of bias transistor is used. This enables generation of PTAT saturation current for current starved inverters, due to dominance of threshold voltage decrease with temperature over mobility decrease. I.Another limitation, process dependency of the sensing characteristics, was overcome through the proposed calibration based compensation technique. A changing Vc proportional to threshold voltage variation with process, process independent bias current and current temperature characteristics were obtained. This compensated for the process variation effects on frequency. Thus, a variable Vc was generated using a reference with low temperature sensitivity of 17.6_V=0C, and resistive divider combinations for various processes. Incorporating this compensation technique we achieved good linearity in sensor characteristics and a maximum temperature error of± 1.60C over the sensing range. The sensor consumes a low power of 0.29mW and also occupies minimal area.

Cette thèse adresse le sujet de la génération de suites binaires aléatoires dans les circuits logiques programmables FPGA et plus particulièrement les suites dont l’origine aléatoire est de nature physique et non algorithmique. De telles suites trouvent une utilisation abondante dans la plupart des protocoles cryptographiques. Un état de l’art portant sur les différentes méthodes de génération de vrai aléa dans les circuits logiques programmables est présenté sous forme d’analyse critique d’articles scientifiques. Une synthèse des différentes tendances dans l’extraction et la génération d’aléa est également présentée. Une campagne d’expériences et de mesures est présentée visant à caractériser les différentes sources de signaux aléatoires disponibles à l’intérieur du FPGA. Des phénomènes intéressants tel le verrouillage de plusieurs oscillateurs en anneau, la dépendance de la source d’aléa vis-à-vis de la logique environnante et la méthodologie de mesure du jitter sont analysés. Plusieurs méthodes nouvelles de génération de suites binaires aléatoires sont décrites. Finalement une méthodologie nouvelle de simulation en VHDL de générateurs complets ainsi qu’un modèle mathématique d’un oscillateur en anneau en tant que source d’aléa sont présentés / This thesis addresses the topic of the generation of random binary streams in FPGA and especially random sequences whose origin is physical and not algorithmic. Such sequences find abundant use in most cryptographic protocols. A state of the art regarding the various methods of generating true randomness in programmable logic is presented as a critical analysis of scientific articles. A synthesis of different trends in the extraction and generation of true randomness is presented. A campaign of experiments and measurements is presented to characterize the different sources of random signals available inside the FPGA. Interesting phenomena such as the locking of several ring oscillators and the sensibility of the source of randomness depending to the surrounding logic activity are reported. Several new methods for generating random binary sequences are described and analyzed. Finally a new simulation methodology in VHDL and a mathematical model of a ring oscillator as a source of randomness for TRNG are presented

Les générateurs de nombres véritablement aléatoires (TRNG) sont des composants cruciaux dans certaines applications cryptographiques sensibles (génération de clés de chiffrement, génération de signatures DSA, etc). Comme il s’agit de composants très bas-niveau, une faille dans le TRNG peut remettre en question la sécurité de tout le système cryptographique qui l’exploite. Alors que beaucoup de principes de TRNG existent dans la littérature, peu de travaux analysent rigoureusement ces architectures en termes de sécurité. L’objectif de cette thèse était d’étudier les avantages des techniques de conception asynchrone pour la conception de générateurs de nombres véritablement aléatoires (TRNG) sûrs et robustes. Nous nous sommes en particulier intéressés à des oscillateurs numériques appelés anneaux auto-séquencés. Ceux-ci exploitent un protocole de requêtes et acquittements pour séquencer les données qui y circulent. En exploitant les propriétés uniques de ces anneaux, nous proposons un nouveau principe de TRNG, avec une étude théorique détaillée sur son fonctionnement, et une évaluation du cœur du générateur dans des cibles ASIC et FPGA. Nous montrons que ce nouveau principe permet non seulement de générer des suites aléatoires de très bonne qualité et avec un très haut débit (>100 Mbit/s), mais il permet aussi une modélisation réaliste de l’entropie des bits de sortie (celle-ci peut être réglée grâce aux paramètres de l’extracteur). Ce travail propose également une méthodologie complète pour concevoir ce générateur, pour le dimensionner en fonction du niveau de bruit dans le circuit, et pour le sécuriser face aux attaques et défaillances / True Random Number Generators (TRNG) are ubiquitous in many critical cryptographic applications (key generation, DSA signatures, etc). While many TRNG designs exist in literature, only a few of them deal with security aspects, which is surprising considering that they are low-level primitives in a cryptographic system (a weak TRNG can jeopardize a whole cryptographic system). The objective of this thesis was to study the advantages of asynchronous design techniques in order to build true random number generators that are secure and robust. We especially focused on digital oscillators called self-timed rings (STR), which use a handshake request and acknowledgement protocol to organize the propagation of data. Using some of the unique properties of STRs, we propose a new TRNG principle, with a detailed theoretical study of its behavior, and an evaluation of the TRNG core in ASICs and FPGAs. We demonstrate that this new principle allows to generate high quality random bit sequences with a very high throughput (> 100 Mbit/s). Moreover, it enables a realistic estimation for the entropy per output bit (this entropy level can be tuned using the entropy extractor parameters). We also present a complete methodology to design the TRNG, to properly set up the architecture with regards to the level of noise in the circuit, and to secure it against attacks and failures