Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life. In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLAB simulation and FPGA simulation to verify our design.

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The problem of the efficient use of Hybrid Automatic-Repeat-reQuest (Hybrid-ARQ) in wireless communication has attracted a considerable amount of research. In this thesis, the use and implementation of turbo codes as the Forward Error Correction (FEC) code for Hybrid-ARQ is investigated. The major accomplishments of the research include both the analysis and implementation of turbo Hybrid-ARQ. The thesis begins by obtaining a tractable bound for the performance of turbo codes with M-ary Quadrature-Amplitude-Modulation (M-ary QAM). The research considers the design problem of turbo coded Hybrid-ARQ optimized for AWGN and fading channels. The design problem of turbo Hybrid-ARQ in wideband channels is considered and an optimization strategy is proposed based on Orthogonal-Frequency-Division- Multiplexing (OFDM). The research also presents a novel rate scalable encoder structure that optimal selects a disparate but optimal pair of component codes given the channel conditions. A second part of the thesis considers the implementation of turbo Hybrid-ARQ in Very Large Scale Integration (VLSI ) systems. A design for a single architecture for Type-I and Type-II turbo Hybrid-ARQ is suggested in addition to approaches for improving performance of the Soft-Output-Viterbi-Algorithm(SOVA) decoder core. The research also proposes a SOVA decoder architecture that exploits reliability information to select between the SOVA and bi-directional SOVA.

Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the total state metric can be effectively reduced by a half with slightly overhead of adders/subtractors. For non-recursive systematic encoding applications, the same design methodology can further reduce the number of arithmetic units required in the soft-output calculating module. Our preliminary experimental result shows that the proposed design methodology can achieve 40% and 13% reduction on the gate count and power dissipation respectively.

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One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor. / En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.

Σε αυτήν την διπλωματική εργασία ασχοληθήκαμε με την υλοποίηση των κριτηρίων έγκυρου τερματισμού του Turbo αποκωδικοποιητή σε συσκευή FPGA. Στο πρώτο κεφάλαιο παρουσιάζουμε το θεωρητικό υπόβαθρο που περιλαμβάνει βασικές έννοιες των ψηφιακών επικοινωνιών και την μαθηματική υποστήριξη του turbo κώδικα. Στο δεύτερο κεφάλαιο παρουσιάζονται τα αποτελέσματα της εξομοίωσης του κώδικα. Στο τρίτο κεφάλαιο παρουσιάζεται αρχιτεκτονική του κυκλώματος που υλοποιεί τον turbo κώδικα τόσο από την πλευρά του κωδικοποιητή όσο και από την πλευρά του αποκωδικοποιητή. Εν συνεχεία, στο κεφάλαιο 4 παρουσιάζεται το προτεινόμενο κριτήριο τερματισμού μαζί με την δική του υλοποίηση καθώς και την υλοποίηση τριών άλλων κριτηρίων. Στο τέλος παρουσιάζουμε τα συμπερασματά μας και τις μετρήσεις μας. / In this thesis we studied the implementation of the termination criteria of the turbo decoder as well as its implementation on the hardware. In the first chapter an introduction to fundamental concepts of digital communication as well as their mathimatical expression. In the second chapter the results of the simulation of the code are presented. In the third chapter the architecture of the turbo encoder and decoder are presented. In the fourth chapter a new termination criterion is presented with the implementation of tree other criteria. Finally we present our conclusions and our measurements.

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