One technique that is used to reduce the errors brought upon signals, when transmitted over noisy channels, is error control coding. One type of such coding, which has a good performance, is turbo coding. In some of the TMS320C64xTM digital signal processors there is a built in coprocessor that performs turbo decoding. This thesis is performed on the account of Communication Developments, within Saab AB and presents an evaluation of this coprocessor. The evaluation deals with both the memory consumption as well as the data rate. The result is also compared to an implementation of turbo coding that does not use the coprocessor. / En teknik som används för att minska de fel som en signal utsätts för vid transmission över en brusig kanal är felrättande kodning. Ett exempel på sådan kodning som ger ett mycket bra resultat är turbokodning. I några digitalsignalprocessorer, av sorten TMS320C64xTM, finns en inbyggd coprocessor som utför turboavkodning. Denna uppsats är utförd åt Communication Development inom Saab AB och presenterar en utvärdering av denna coprocessor. Utvärderingen avser såväl minnesförbrukning som datatakt och innehåller även en jämförelse med en implementering av turbokodning utan att använda coprocessorn.

Research indicates that multiprocessor-based architectures will provide a flexible alternative to hard-wired application-specific integrated circuits (ASICs) suitable to implement the multitude of wireless standards required by mobile devices, while meeting their strict area and power requirements. This shift in design philosophy has led to the software-defined radio (SDR) paradigm, where a significant portion of a wireless standard's physical layer is implemented in software, allowing multiple standards to share a common architecture. Turbo codes offer excellent error-correcting performance, however, turbo decoders are one of the most computationally complex baseband tasks of a wireless receiver. Next generation wireless standards such as Worldwide Interoperability for Microwave Access (WiMAX), support enhanced double-binary turbo codes, which offer even better performance than the original binary turbo codes, at the expense of additional complexity. Hence, the design of efficient double-binary turbo decoder software is required to support wireless standards in a SDR environment. This thesis describes the optimization, parallelization, and simulated performance of a software double-binary turbo decoder implementation supporting the WiMAX standard suitable for SDR. An adapted turbo decoder is implemented in the C language, and numerous software optimizations are applied to reduce its overall computationally complexity. Evaluation of the software optimizations demonstrated a combined improvement of at least 270% for serial execution, while maintaining good bit-error rate (BER) performance. Using a customized multiprocessor simulator, special instruction support is implemented to speed up commonly performed turbo decoder operations, and is shown to improve decoder performance by 29% to 40%. The development of a flexible parallel decoding algorithm is detailed, with multiprocessor simulations demonstrating a speedup of 10.8 using twelve processors, while maintaining good parallel efficiency (above 89%). A linear-log-MAP decoder implementation using four iterations was shown to have 90% greater throughput than a max-log-MAP decoder implementation using eight iterations, with comparable BER performance. Simulation also shows that multiprocessor cache effects do not have a significant impact on parallel execution times. An initial investigation into the use of vector processing to further enhance performance of the parallel decoder software reveals promising results. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2009-09-25 16:22:47.288

Σε αυτήν την διπλωματική εργασία ασχοληθήκαμε με την υλοποίηση των κριτηρίων έγκυρου τερματισμού του Turbo αποκωδικοποιητή σε συσκευή FPGA. Στο πρώτο κεφάλαιο παρουσιάζουμε το θεωρητικό υπόβαθρο που περιλαμβάνει βασικές έννοιες των ψηφιακών επικοινωνιών και την μαθηματική υποστήριξη του turbo κώδικα. Στο δεύτερο κεφάλαιο παρουσιάζονται τα αποτελέσματα της εξομοίωσης του κώδικα. Στο τρίτο κεφάλαιο παρουσιάζεται αρχιτεκτονική του κυκλώματος που υλοποιεί τον turbo κώδικα τόσο από την πλευρά του κωδικοποιητή όσο και από την πλευρά του αποκωδικοποιητή. Εν συνεχεία, στο κεφάλαιο 4 παρουσιάζεται το προτεινόμενο κριτήριο τερματισμού μαζί με την δική του υλοποίηση καθώς και την υλοποίηση τριών άλλων κριτηρίων. Στο τέλος παρουσιάζουμε τα συμπερασματά μας και τις μετρήσεις μας. / In this thesis we studied the implementation of the termination criteria of the turbo decoder as well as its implementation on the hardware. In the first chapter an introduction to fundamental concepts of digital communication as well as their mathimatical expression. In the second chapter the results of the simulation of the code are presented. In the third chapter the architecture of the turbo encoder and decoder are presented. In the fourth chapter a new termination criterion is presented with the implementation of tree other criteria. Finally we present our conclusions and our measurements.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a turbo decoder based on the log-MAP algorithm. Our turbo decoder has two component log-MAP decoders, which perform the decoding process alternatively. Two major ideas for low-power design are employment of a variable number of iterations during the decoding process and shutdown of inactive component decoders. The number of iterations during decoding is determined dynamically according to the channel condition to save power. When a component decoder is inactive, the clocks and spurious inputs to the decoder are blocked to reduce power dissipation. We followed the standard cell design approach to design the proposed turbo decoder. The decoder was described in VHDL, and then synthesized to measure the performance of the circuit in area, speed and power. Our decoder achieves good performance in terms of bit error rate. The two proposed methods significantly reduce power dissipation and energy consumption. / Master of Science

Pour permettre l’accroissement de débit et de robustesse dans les futurs systèmes de communication sans fil, les processus itératifs sont de plus considérés dans les récepteurs. Cependant, l’adoption d’un traitement itératif pose des défis importants dans la conception du récepteur. Dans cette thèse, un récepteur itératif combinant les techniques de détection multi-antennes avec le décodage de canal est étudié. Trois aspects sont considérés dans un contexte MIMOOFDM: la convergence, la performance et la complexité du récepteur. Dans un premier temps, nous étudions les différents algorithmes de détection MIMO à décision dure et souple basés sur l’égalisation, le décodage sphérique, le décodage K-Best et l’annulation d’interférence. Un décodeur K-best de faible complexité (LC-K-Best) est proposé pour réduire la complexité sans dégradation significative des performances. Nous analysons ensuite la convergence de la combinaison de ces algorithmes de détection avec différentes techniques de codage de canal, notamment le décodeur turbo et le décodeur LDPC en utilisant le diagramme EXIT. En se basant sur cette analyse, un nouvel ordonnancement des itérations internes et externes nécessaires est proposé. Les performances du récepteur ainsi proposé sont évaluées dans différents modèles de canal LTE, et comparées avec différentes techniques de détection MIMO. Ensuite, la complexité des récepteurs itératifs avec différentes techniques de codage de canal est étudiée et comparée pour différents modulations et rendement de code. Les résultats de simulation montrent que les approches proposées offrent un bon compromis entre performance et complexité. D’un point de vue implémentation, la représentation en virgule fixe est généralement utilisée afin de réduire les coûts en termes de surface, de consommation d’énergie et de temps d’exécution. Nous présentons ainsi une représentation en virgule fixe du récepteur itératif proposé basé sur le décodeur LC K-Best. En outre, nous étudions l’impact de l’estimation de canal sur la performance du système. Finalement, le récepteur MIMOOFDM itératif est testé sur la plateforme matérielle WARP, validant le schéma proposé. / Recently, iterative processing has been widely considered to achieve near-capacity performance and reliable high data rate transmission, for future wireless communication systems. However, such an iterative processing poses significant challenges for efficient receiver design. In this thesis, iterative receiver combining multiple-input multiple-output (MIMO) detection with channel decoding is investigated for high data rate transmission. The convergence, the performance and the computational complexity of the iterative receiver for MIMO-OFDM system are considered. First, we review the most relevant hard-output and soft-output MIMO detection algorithms based on sphere decoding, K-Best decoding, and interference cancellation. Consequently, a low-complexity K-best (LCK- Best) based decoder is proposed in order to substantially reduce the computational complexity without significant performance degradation. We then analyze the convergence behaviors of combining these detection algorithms with various forward error correction codes, namely LTE turbo decoder and LDPC decoder with the help of Extrinsic Information Transfer (EXIT) charts. Based on this analysis, a new scheduling order of the required inner and outer iterations is suggested. The performance of the proposed receiver is evaluated in various LTE channel environments, and compared with other MIMO detection schemes. Secondly, the computational complexity of the iterative receiver with different channel coding techniques is evaluated and compared for different modulation orders and coding rates. Simulation results show that our proposed approaches achieve near optimal performance but more importantly it can substantially reduce the computational complexity of the system. From a practical point of view, fixed-point representation is usually used in order to reduce the hardware costs in terms of area, power consumption and execution time. Therefore, we present efficient fixed point arithmetic of the proposed iterative receiver based on LC-KBest decoder. Additionally, the impact of the channel estimation on the system performance is studied. The proposed iterative receiver is tested in a real-time environment using the MIMO WARP platform.