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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Sistemas de Ecualización Turbo, Usando LOG-MAP y LDPC no Binario

Yáñez Azúa, Gonzalo Antonio January 2008 (has links)
El creciente avance de las telecomunicaciones durante estos últimos años, ha despertado el interés de muchos investigadores en conseguir más y mejores técnicas que permitan establecer comunicaciones inalámbricas robustas y que a su vez, soporten grandes flujos de información a alta velocidad. No obstante, la utilización de un canal inalámbrico para el envío y recepción de señales, introduce efectos indeseados tales como interferencia y ruido, debido a que entre el emisor y el receptor se interponen diferentes agentes que se comportan de aletoriamente. Es así como se han desarrollado métodos que han despertado gran interés entre los investigadores, debido a la obtención de resultados sorprendentes. Entre estos métodos destacan el algoritmo MAP y los códigos LDPC. El primero puede ser utilizado tanto en el aspecto de la ecualización de señales o en la decodificación de señales, mientras que el segundo se utiliza específicamente para codificar y decodificar señales. De este modo, el objetivo principal de esta memoria es unir estos dos algoritmos para que trabajen de forma iterativa, utilizando la información proporcionada por el ecualizador para mejorar el proceso de decodificación y a su vez, realizar el proceso de ecualización utilizando la información del decodificador. A este sistema retroalimentado se le llama Esquema Turbo. Además, se plantea el algoritmo para lenguajes no binarios. Para realizar este trabajo, primeramente se hizo un desglose de un sistema de comunicaciones actual, reconociendo cada uno de los bloques componentes, analizando su funcionamiento teórico, introduciendo modificaciones según corresponda y a partir de este análisis obtiene un diagrama de bloques que resume el funcionamiento general del algoritmo propuesto. Seguidamente se realizan pruebas a pequeña escala, utilizando un modelo de canal TDL Gaussiano de tres derivaciones, capaz de emular el comportamiento de una señal bajo interferencia y ruido, con el objetivo de demostrar el correcto funcionamiento del algoritmo y su convergencia, para posteriormente someter el esquema a transmisiones de grandes bloques de información, midiendo su desempeño bajo distintos escenarios y estudiando la tasa de símbolos errados (SER) variando la razón señal ruido (SNR). Los resultados obtenidos de esta investigación dicen que este algoritmo es capaz de lograr una corrección completa en señales pequeñas, incluso bajo condiciones en que de SNR se reduce hasta 5 dB para 7 iteraciones. Sin embargo, al momento de enviar bloques de información de tamaño mucho mayor (105 símbolos), el algoritmo presenta un piso de SNR de 10 dB, ya que al aumentarlo por sobre ese valor no se lograba mejoramiento de decodificación, debido a que se utilizó un esquema de codificación de bloques con matrices pequeñas. Esto se explica justamente porque la elaboración de matrices de codificación para códigos LDPC no binarios, para bloques grandes de información, es un tema de investigación que no se encuentra resuelto hasta la fecha.
2

Reconfigurable Turbo Decoding for 3G Applications.

Chaikalis, Costas, Noras, James M. January 2004 (has links)
No / Software radio and reconfigurable systems represent reconfigurable functionalities of the radio interface. Considering turbo decoding function in battery-powered devices like 3GPP mobile terminals, it would be desirable to choose the optimum decoding algorithm: SOVA in terms of latency, and log-MAP in terms of performance. In this paper it is shown that the two algorithms share common operations, making feasible a reconfigurable SOVA/log-MAP turbo decoder with increased efficiency. Moreover, an improvement in the performance of the reconfigurable architecture is also possible at minimum cost, by scaling the extrinsic information with a common factor. The implementation of the improved reconfigurable decoder within the 3GPP standard is also discussed, considering different scenarios. In each scenario various frame lengths are evaluated, while the four possible service classes are applied. In the case of AWGN channels, the optimum algorithm is proposed according to the desired quality of service of each class, which is determined from latency and performance constraints. Our analysis shows the potential utility of the reconfigurable decoder, since there is an optimum algorithm for most scenarios.
3

On a turbo decoder design for low power dissipation

Fei, Jia 21 July 2000 (has links)
A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a turbo decoder based on the log-MAP algorithm. Our turbo decoder has two component log-MAP decoders, which perform the decoding process alternatively. Two major ideas for low-power design are employment of a variable number of iterations during the decoding process and shutdown of inactive component decoders. The number of iterations during decoding is determined dynamically according to the channel condition to save power. When a component decoder is inactive, the clocks and spurious inputs to the decoder are blocked to reduce power dissipation. We followed the standard cell design approach to design the proposed turbo decoder. The decoder was described in VHDL, and then synthesized to measure the performance of the circuit in area, speed and power. Our decoder achieves good performance in terms of bit error rate. The two proposed methods significantly reduce power dissipation and energy consumption. / Master of Science
4

VLSI Implementation of Key Components in A Mobile Broadband Receiver

Huang, Yulin January 2009 (has links)
<p>Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.</p>
5

VLSI Implementation of Key Components in A Mobile Broadband Receiver

Huang, Yulin January 2009 (has links)
Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.
6

Turbo Decoding With Early State Decisions

Lindblom, Johannes January 2008 (has links)
<p>Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX).</p><p>There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many variables in the decoder the decoding circuit will consume a lot of power due to memory accesses and internal communication. One way in which this can be reduced is to make early decisions.</p><p>In this work I have focused on making early decision of the encoder states. One major part of the work was also to be sure that the expressions were written in a way that as few variables as possible are needed. A termination condition is also introduced. Simulations based on estimations of the number of memory accesses, shows that the number of memory accesses will significantly decrease.</p>
7

Turbo Decoding With Early State Decisions

Lindblom, Johannes January 2008 (has links)
Turbo codes was first presented in 1993 by C. Berrou, A. Glavieux and P. Thitimajshima. Since then this class of error correcting codes has become one of the most popular, because of its good properties. The turbo codes are able to come very close to theoretical limit, the Shannon limit. Turbo codes are for example used in the third generation of mobile phone (3G) and in the standard IEEE 802.16 (WiMAX). There are some drawbacks with the algorithm for decoding turbo codes. The deocoder uses a Maximum A Posteriori (MAP) algorithm, which is a complex algorith. Because of the use of many variables in the decoder the decoding circuit will consume a lot of power due to memory accesses and internal communication. One way in which this can be reduced is to make early decisions. In this work I have focused on making early decision of the encoder states. One major part of the work was also to be sure that the expressions were written in a way that as few variables as possible are needed. A termination condition is also introduced. Simulations based on estimations of the number of memory accesses, shows that the number of memory accesses will significantly decrease.
8

Energy-Efficient Turbo Decoder for 3G Wireless Terminals

Al-Mohandes, Ibrahim January 2005 (has links)
Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.
9

Energy-Efficient Turbo Decoder for 3G Wireless Terminals

Al-Mohandes, Ibrahim January 2005 (has links)
Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (3G) wireless high-speed (up to 2 Mbps) data services (cdma2000 in North America and W-CDMA in Japan and Europe). For battery-powered hand-held wireless terminals, energy consumption is a major concern. In this thesis, a new design for an energy-efficient turbo decoder that is suitable for 3G wireless high-speed data terminals is proposed. The Log-MAP decoding algorithm is selected for implementation of the constituent Soft-Input/Soft-Output (SISO) decoder; the algorithm is approximated by a fixed-point representation that achieves the best performance/complexity tradeoff. To attain energy reduction, a two-stage design approach is adopted. First, a novel dynamic-iterative technique that is appropriate for both good and poor channel conditions is proposed, and then applied to reduce energy consumption of the turbo decoder. Second, a combination of architectural-level techniques is applied to obtain further energy reduction; these techniques also enhance throughput of the turbo decoder and are area-efficient. The turbo decoder design is coded in the VHDL hardware description language, and then synthesized and mapped to a 0. 18<i>&mu;</i>m CMOS technology using the standard-cell approach. The designed turbo decoder has a maximum data rate of 5 Mb/s (at an upper limit of five iterations) and is 3G-compatible. Results show that the adopted two-stage design approach reduces energy consumption of the turbo decoder by about 65%. A prototype for the new turbo codec (encoder/decoder) system is implemented on a Xilinx XC2V6000 FPGA chip; then the FPGA is tested using the CMC Rapid Prototyping Platform (RPP). The test proves correct functionality of the turbo codec implementation, and hence feasibility of the proposed turbo decoder design.
10

Επαναληπτική αποκωδικοποίηση χωροχρονικών κωδικών (space-time codes) σε συστήματα ορθογώνιας πολυπλεξίας φερουσών: αναπαράσταση δεδομένων και πολυπλοκότητα

Αγγελόπουλος, Aπόστολος 06 August 2007 (has links)
Η χρήση πολλαπλών κεραιών παίζει πλέον ένα πολύ σημαντικό ρόλο στη βελτίωση των ραδιοτηλεπικοινωνιών. Για το λόγο αυτό, ο τομέας των τηλεπικοινωνιακών συστημάτων πολλαπλών κεραιών μετάδοσης – λήψης (συστήματα ΜΙΜΟ) βρίσκεται στο προσκήνιο της ασύρματης έρευνας. Πρόσφατα, αποτελέσματα ερευνών έδειξαν ότι υπάρχει δυνατότητα αύξησης της χωρητικότητας στα ασύρματα τηλεπικοινωνιακά συστήματα χρησιμοποιώντας τεχνικές διαφοροποίησης μεταξύ πομπού – δέκτη (antenna diversity), δηλαδή δημιουργίας πολλαπλών ανεξάρτητων καναλιών ανάμεσα τους. Στην παρούσα εργασία μελετούνται τεχνικές κωδικοποίησης που εκμεταλλεύονται τη χωρική διαφοροποίηση κάνοντας χρήση χωροχρονικών κωδικών (space – time coding). Η μελέτη εστιάζεται στη χρήση χωροχρονικών κωδικών ανά μπλοκ από την πλευρά του πομπού, εξαιτίας της απλότητας υλοποίησης τους καθώς και της ικανότητας υποστήριξης πολλαπλών κεραιών από τη πλευρά του σταθμού βάσης. Η ανάλυσή τους γίνεται με βάση την εφαρμογή τους σε συστήματα που χρησιμοποιούν διαμόρφωση με πολυπλεξία ορθογώνιων φερουσών (OFDM). Η διαμόρφωση αυτή επιλέχθηκε γιατί υποστηρίζει υψηλούς ρυθμούς δεδομένων στα ασύρματα συστήματα και δείχνει άριστη συμπεριφορά σε κανάλια με επιλεκτική παραμόρφωση στη συχνότητα. Στη συνέχεια μελετώνται αλγόριθμοι επαναληπτικής αποκωδικοποίησης, δίνοντας έμφαση σε ένα ευρέως διαδεδομένο αλγόριθμο, τον Μέγιστο εκ των Υστέρων (MAP). Αναλύονται διεξοδικά τα βήματα του, καθώς και διάφορες τροποποιήσεις – βελτιστοποιήσεις του. Οι επαναληπτικοί αλγόριθμοι αποκωδικοποίησης αποτελούν πλέον ένα πολύ ισχυρό εργαλείο για την αποκωδικοποίηση Forward Error Correction κωδικοποιήσεων με χρήση συνελικτικών κωδικών, προσδίδοντας στα συστήματα αποδόσεις κοντά στο όριο του Shannon. Τέλος, πραγματοποιούνται κατάλληλες υλοποιήσεις που προέκυψαν από το συνδυασμό των εν λόγω αλγορίθμων επαναληπτικής αποκωδικοποίησης με τους χωροχρονικούς κώδικες ανά μπλοκ πάνω σε ένα σύστημα κεραιών με χρήση OFDM. Γίνεται σύγκριση της απόδοσης των συστημάτων αυτών με βάση την αντίστοιχη υλοποίηση του εκάστοτε αλγορίθμου επαναληπτικής αποκωδικοποίησης και μελετούνται σε βάθος διάφορες τροποποιήσεις που μπορούν δεχθούν με κριτήριο τη χαμηλή πολυπλοκότητα υλοποίησης. Για την αξιολόγηση της απόδοσης, γίνεται μία περαιτέρω σύγκριση με χρήση αναπαράστασης σταθερής υποδιαστολής και εξάγονται σειρά συμπερασμάτων από τις πειραματικές μετρήσεις που προέκυψαν. / The use of multiple antennas is an essential issue in telecommunications, nowadays. So, multiple input – multiple output systems (MIMO) has attracted a lot of attention in wireless research. Lately, it has been shown that it can be an improvement in the capacity of wireless communication systems by using antenna diversity, that’s different independent channels between transmitter and receiver. In this thesis, we study coding techniques that exploit space diversity by using space – time codes. Particularly, we focus on space – time block coding (STBC) from the transmitter’s point of view, because of the simplicity of its implementation and the ability to support multiple antennas at the base stations. The analysis is based on the systems that use Orthogonal Frequency Division Multiplexing Systems (OFDM). This technique was chosen because it can support high data rates and it behaves very well in a frequency selective fading channel. Moreover, we study iterative decoding algorithms and we focus on a very well known algorithm, the Maximum A Posteriori (MAP). There, we analyze its steps and its modifications and improvements. The iterative decoding algorithms are a cornerstone on decoding Forward Error Correction codes, such as Convolutional codes, almost reaching the Shannon limit. Finally, there are different kinds of implementations using suitable iterative decoding algorithms in concatenation with space – time block coding with antennas and ODFM. We compare the performance of the corresponding systems and investigate the complexity trying to maintain it in a low level. For a thorough investigation, we also use fixed point arithmetic in these implementations.

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