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1	On a Viterbi decoder design for low power dissipation Ranpara, Samirkumar Dhirajlal 29 April 1999 (has links) Convolutinal coding is a coding scheme often employed in deep space communications and recently in digital wireless communications. Viterbi decoders are used to decode convolutional codes. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. With the proliferation of battery powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of Viterbi decoders for wireless communications applications. In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment. We considered two methods, clock-gating and toggle-filtering, in our design. A Viterbi decoder consists of five blocks. The clock-gating was applied to the survivor path storage block and the toggle-filtering to the trace-back block of a Viterbi decoder. We followed the standard cell design approach to implement the design. The behavior of a Viterbi decoder was described in VHDL, and then the VHDL description was modified to embed the low-power design. A gate level circuit was obtained from the behavioral description through logic synthesis, and a full scan design was incorporated into the gate level circuit to ease testing. The gate level circuit was placed and routed to generate a layout of the design. Our experimental result shows the proposed design reduces the power dissipation of a Viterbi decoder by about 42 percent compared with the on without considering the low-power design. / Master of Science Full scan Viterbi decoder Low power Synopsys
2	Vaizdų atpažinimo sistemos projektavimas ir tyrimas / Image processing system design and analysis Jonutis, Vytautas, Jaraminas, Mindaugas 11 August 2008 (has links) Darbe analizuojamas vaizdo apdorojimo sistemos modelis, kuris yra modeliuojamas. Pradinė modelio specifikacija yra aprašoma funkciniame lygyje. Modelio architektūrai modeliuoti mes naudojame transakcijų lygio SystemC, naudodamiesi ja mes galime greitai ir patogiai nustatyti, kokia turėtų būti modeliuojamos sistemos architektūra. Funkcinis modelis yra transformuojamas į sisteminį lygį naudojantis SystemC transakcijų modeliavimo kalba. Naudojantis pradine specifikacija ir TLM modeliu pereiname prie sintezuojamo aprašo. Transformuodami pradinį modelį aukštame abstrakcijos lygyje, mes sprendžiame sistemos architektūros problemą. Transformuodami aukšto lygio modelį į SystemC sintezuojamą aprašą, mes sprendžiame kintamųjų ir algoritmų transformavimo problemas. / In this work we analyzing video preprocessing system model. Primary model specifications are described in functional level. It is hard to decide what system architecture should be, so we used SystemC TLM modeling language, because it gives us easier way to change system architecture Using SystemC transaction level modeling (TLM) the functional primary specification are transformed from functional model to system level. To get synthesizable model we use primary specification and TLM model. We solve many system architecture problems while we where working on primary model transformation to high abstraction system. Transforming high abstraction level model to SystemC synthesizable code we solve variables selection problems and algorithms conversation problem. Informatics TLM SysytemC Vaizdų atpažinties sistemos RTL Synopsys TLM SysytemC Pattern recognition systems RTL Synopsys
3	On the Characterization of Library Cells Sulistyo, Jos Budi 01 September 2000 (has links) In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method. / Master of Science VLSI Cadence Characterization Synopsys Timing Model Power Estimation Standard Cell
4	Ανάπτυξη εργαλείων σχεδίασης και ελέγχου ορθής λειτουργίας κυκλωμάτων Μαυρακάκης, Ιωάννης Κ. 03 March 2009 (has links) - / - Κυκλώματα 004.66 Timing analyzer Structural verilog Synopsys Hope
5	On a turbo decoder design for low power dissipation Fei, Jia 21 July 2000 (has links) A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood (ML) decoding algorithm. While the MAP algorithm offers better performance than the ML algorithm, the computation is complex and not suitable for hardware implementation. The log-MAP algorithm, which performs necessary computations in the logarithm domain, greatly reduces hardware complexity. With the proliferation of the battery powered devices, power dissipation, along with speed and area, is a major concern in VLSI design. In this thesis, we investigated a low-power design of a turbo decoder based on the log-MAP algorithm. Our turbo decoder has two component log-MAP decoders, which perform the decoding process alternatively. Two major ideas for low-power design are employment of a variable number of iterations during the decoding process and shutdown of inactive component decoders. The number of iterations during decoding is determined dynamically according to the channel condition to save power. When a component decoder is inactive, the clocks and spurious inputs to the decoder are blocked to reduce power dissipation. We followed the standard cell design approach to design the proposed turbo decoder. The decoder was described in VHDL, and then synthesized to measure the performance of the circuit in area, speed and power. Our decoder achieves good performance in terms of bit error rate. The two proposed methods significantly reduce power dissipation and energy consumption. / Master of Science Branch metric State metric Low power Synopsys Log-likelihood ratio Log-MAP Turbo decoder
6	Flujo de Diseño de Circuitos Integrados Digitales Aplicado al Desarrollo de un Controlador USB 2.0 Díaz Pérez, Daniel Alfonso January 2010 (has links) El presente trabajo de título tiene como objetivo principal la exposición del flujo de procesos involucrado en el diseño de un circuito integrado digital. Como consecuencia de ésto, se espera poder demostrar y motivar a explorar esta área en Chile, partiendo por el entorno más cercano: el Departamento de Ingeniería Eléctrica de la Facultad de Ciencias Físicas y Matemáticas de la Universidad de Chile. Para conseguir este objetivo, se diseña un controlador USB 2.0 desde la asimilación de su protocolo para el modelamiento de una solución, hasta el esquemático de la disposición física del circuito resultante. El flujo de diseño consiste principalmente en: a partir de una idea, generada por una necesidad del mercado o bien por una razón académica, determinar sus especificaciones eléctricas y dividir sus funcionalidades; caracterizar el circuito utilizando un lenguaje de descripción de hardware, para esta memoria, Verilog HDL; traducir la descripción del circuito a una lista de compuertas lógicas reales interconectadas; y finalmente, utilizando la representación física de cada compuerta y conexiones, producir un plano físico del circuito. El desarrollo del controlador es guiado y facilitado por las herramientas de diseño de Synopsys®. El resultado final es un informe que reúne los principales conceptos comprometidos en cada etapa del diseño, junto con su aplicación al modelamiento de un controlador USB 2.0. Aunque el uso de las herramientas de diseño no es detallado, los pasos realizados para cada proceso están basados en los flujos de diseño específicos de cada una de ellas. Respecto a lo anterior, se entrega como resultado un CD que contiene los módulos Verilog del controlador, la lista de compuertas interconectadas y archivos guión que contienen las principales instrucciones ejecutadas en las herramientas de Synopsys®. USB es un protocolo de comunicación de mediana complejidad que requiere de un equipo de diseñadores para desarrollarlo con profundidad en todos sus aspectos. A su vez, el flujo de diseño de circuitos integrados posee una gran cantidad de conceptos que deben ser manejados para realizar un trabajo de nivel profesional, probablemente con especialistas en cada etapa. Se concluye que el diseño de circuitos integrados, sin considerar la fabricación, es posible de realizar completamente en Chile, considerando la existencia de las herramientas adecuadas y profesionales especializados o con interés en hacerlo. Electricidad Circuitos integrados digitales Electrónica digital Controlador USB 2.0 Diseño de synopsys
7	An 8 bit Serial Communication module Chip Design Using Synopsys tools and ASIC Design Flow Methodology Munugala, Anvesh 23 May 2018 (has links) No description available. Computer Engineering Electrical Engineering Serial communication ASIC design Synopsys tools FPGA UART Fabrication Design for Testability 500 nm CMOS technology
8	Caractérisation basse fréquence et simulation physique de transistors bipolaires hétérojonction en vue de l'analyse du bruit GR assisté par pièges / Low frequency characterization and physical simulation of heterojunction bipolar transistors for the analysis of the noise GR assisted by traps Al Hajjar, Ahmad 19 May 2016 (has links) Ce travail présente le développement d’un banc de mesure thermique, pour la mesure : de réseaux I (V), d’impédance basse fréquence et de bruit basse fréquence des composants semi-conducteurs. Le banc de mesure de bruit BF est composé d’un amplificateur de tension faible bruit, d’un amplificateur transimpédance, d’un analyseur FFT et d’un support thermique. Ce banc a permis d’extraire les sources de bruit en courants équivalentes aux accès du transistor pour différentes densités de courant et à différentes températures. Dans le but de calculer l’énergie d’activation et la section de capture des pièges grâce à la localisation des fréquences de coupures de bruit GR dans la technologie du TBH InGaP/GaAs. Dans un deuxième temps, nous avons étudié le bruit basse fréquence dans le transistor InGaP/GaAs et les jonctions base émetteur, base collecteur et la résistance TLM par le moyen de simulation physique et de mesure de densité spectrale de puissance de bruit basse fréquence. Grâce à ces mesures, nous avons pu extraire les sources de bruit internes locales commandées et non commandées. Cette extraction nous a permis de calculer les énergies d’activations, les sections de capture et de valider la simulation physique. / This work presents the development of a thermal test bench for I(V) characteristics, for low frequency impedance and for low frequency noise of semiconductor components. This thermal bench for low frequency noise measurement is composed of a low-noise voltage amplifier, a low-noise transimpedance amplifier, an FFT vector signal analyzer and a thermal chuck. This measurement bench has allowed to extract the current noise sources equivalent to the access transistor at different current densities and at different temperatures. In order to calculate the activation energy and the capture cross section of traps thanks to the localization of the cutoff frequency of GR noise in HBT InGaP / GaAs technology. Secondly, we studied the low frequency noise in the transistor InGaP / GaAs and the differents junctions: emitter base, collector base and the base represented by the TLM resistance using physical simulations and measurements of low-frequency noise power spectrum density. Using this measurements, we extract the controlled and not controlled local internal noise sources. The extraction has allowed us to calculate the activation energy, the capture cross sections and validate the physical simulation. Bruit basse fréquence Impédance basse fréquence Composants semi-conducteurs Pièges Activation d'énergie Synopsys Sentaurus Simulation physique TBH HEMT CMOS BiCMOS LDMOS Low frequency noise Low frequency impedance Semiconductor components Traps Activation energy Synopsys Sentaurus Physical simulation HBT HEMT CMOS BiCMOS LDMOS 621.381 5
9	Evangeliar. Aarbechtsgrupp "Iwwersetzung vun der Bibel op Lëtzebuergesch" (2009) : Luxembourg : Archevêché / Saint-Paul : considérations historiques, théologiques et exégétiques appliquées à la traduction de l'évangéliaire en luxembourgeois / Evangeliar. Work-group 'Translation of the Bible into Luxembourgish' (2009) : Luxembourg : Archbishopric / Saint-Paul : historical, theological and exegetical considerations applied to the translation of the evangeliary into Luxembourgish Biver-Pettinger, Francoise 24 September 2015 (has links) En 2009 fut édité l’Evangeliar, la première traduction en luxembourgeois des évangiles lus pendant la liturgie de l’Église latine. Dans l’introduction, la présente thèse décrit le contexte historique, ecclésial et national, et la situation des langues dans laquelle les fidèles catholiques ont pratiqué leur religion de 1815 à nos jours. Ensuite, cette étude s’enquiert de l’influence de l’institution Église sur les traductions bibliques liturgiques actuelles, y compris l’Evangeliar. Cette influence peut s’exercer par le Magistère, par la tradition scripturaire ou par l’usage liturgique.Dans le deuxième chapitre, la traduction de Mc 1, 1-45 est revue verset par verset pour discuter la méthode et les critères retenus dans son élaboration. Ceci afin de déceler les pièges linguistiques, exégétiques, théologiques, voire culturels et de sonder les limites d’une traduction des évangiles en luxembourgeois. Dans la conclusion, où convergent les différentes pistes suivies dans la thèse, sont intégrés certains éléments en vue d’une recherche ultérieure sur la traduction de μετανοέω et de μετάνοια en général et dans l’Evangeliar plus particulièrement. / In 2009, the Evangeliar was published in Luxembourgish for the first time, containing the most-read Gospels of the Roman-Catholic liturgical tradition.In the introductory part, this thesis describes the historical, ecclesiastical, national, as well as linguistic background within which the faithful practised their religion from 1815 to the present day. Following on from there, it elucidates the influence of the Roman-Catholic church, as an institution, on contemporary biblical and liturgical translations, including the Evangeliar. This influence can originate from within the practice of Magisterium, scriptural tradition, or liturgical usage.In the second chapter, the translation of Mark 1, 1-45 is revised verse for verse in order to discuss the method as well as the criteria used in its development, with the aim of revealing traps of various kinds: linguistic, exegetical, theological, maybe even cultural, and furthermore to sound out the limitations of a translation into Luxembourgish of the Gospels. The conclusion, in which the various inquiry elements converge, also contains several elements conducive to further research on the translation of μετανοέω and of μετάνοια in general and in the Evangeliar in particular. Concordance, Critères Evangeliar Évangiles Influence Jérôme Liturgiam authenticam Luc Luxembourgeois Magistère Marc Matthieu Méthode Nestlé-Aland Synopse Tradition scripturaire Traduction biblique Traduction liturgique de la Bible Usage liturgique Vocabulaire théologique traditionnel Vulgate Μετανοέω Μετάνοια Concordance Criteria Evangeliar Gospels Influence Liturgiam authenticam Luke Luxembourgish Magisterium Mark Matthew Method Nestlé-Aland Scriptural tradition St. Jerome Synopsys Liturgical translation of the Bible Liturgical usage Traditional theological vocabulary Vulgate Μετανοέω Μετάνοια 243 248.4 439

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