As Moore's law continues to 20nm and below, traditional CMOS device faces severe short channel effects. Industry is switching from traditional CMOS to FinFET in order to keep Moore's law alive. Due to the three-dimensional structure of FinFET, many challenges need to be solved. After that, FinFET will finally be able to replace traditional CMOS in the semiconductor industry. This thesis discusses the manufacturing challenges of FinFET. In addressing these challenges, characterization of the FinFET standard cells has been done. The characterization is based on saturation current, leakage current, implantation angle and the average edge placement error at metal one layer. Three design variables, including the metal pitch, the fin pitch and the fin width are optimized to achieve better design quality. Standard cell library which contains combinatorial cells as well as sequential cells are characterized and optimized. Two optimization scenarios are included in the final results. One is performance driven, optimizing the saturation current and the leakage current, while the other is manufacturability driven, optimizing the implantation angle and the average EPE. The optimization results show the tradeoff between performance and manufacturability. / text

<p>This master thesis describes the creation of a fully parameterizable design tool, intended for automatic generation of standard cell layouts from basic schematic information. The thesis covers general background on programs for automatic layout generation, standard cells and basics in IC design. Algorithms commonly used in various parts of such programs are presented, and the ones used to implement the tool are described in depth.</p>

<p>This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it.</p><p>It also consists of an evaluation of a Place and Route tool, telling the discovered problems with it and ideas for solving them.There is also several different descriptions of the code that implements the Place and Route tool.</p>

This master thesis describes the creation of a fully parameterizable design tool, intended for automatic generation of standard cell layouts from basic schematic information. The thesis covers general background on programs for automatic layout generation, standard cells and basics in IC design. Algorithms commonly used in various parts of such programs are presented, and the ones used to implement the tool are described in depth.

This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it. It also consists of an evaluation of a Place and Route tool, telling the discovered problems with it and ideas for solving them.There is also several different descriptions of the code that implements the Place and Route tool.

With the rapid progress in manufacturing technology, the chip design is more and more complicated day by day. As a result, the circuit design with standard cell library becomes more significant. Standard cell is universally applied to cell-based design and the designer can complete their design quickly by using of the elements in standard cell library through cell-based design flow. Therefore, it is indispensable for VLSI design to utilize standard cell library for circuit design. Moreover, the low power design is getting increasingly important in the circuit design. Therefore, we design the cells with particular function and add them into the standard cell library so that the low power design can be more well-designed. In this thesis, we design and and the transmission gate into the standard cell library. In addition, we design two types of standard cells with TSMC 0.13£gm technology: a low-overhead latch and a modified transmission-gate based full adder. They are applied to design different low power multipliers with cell-based design flow and full custom design flow. Experimental results show that our proposed standard cells can reduce the power consumption of the entire multiplier efficiently.

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In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method. / Master of Science

Essa tese introduz um conjunto de algoritmos baseados em grafos para o mapeamento eficiente de circuitos VLSI com células simples. Os algoritmos propostos se baseiam em minimizar de maneira eficiente o número de elementos lógicos usados na implementação do circuito. Posteriormente, uma quantidade significativa de esforço é aplicada na minimização do número de inversores entre esses elementos lógicos. Por fim, essa representação lógica é mapeada para circuitos compostos somente por células NAND e NOR de duas entradas, juntamente com inversores. Células XOR e XNOR de duas entradas também podem ser consideradas. Como nós também consideramos circuitos sequenciais, flips-flops também são levados em consideração. Com o grande esforço de minimização de elementos lógicos, o circuito gerado pode conter algumas células com um fanout impraticável para os nodos tecnológicos atuais. Para corrigir essas ocorrências, nós propomos um algoritmo de limitação de fanout que considera tanto a área sendo utilizada pelas células quanto a sua profundidade lógica. Os algoritmos propostos foram aplicados sobre um conjunto de circuitos de benchmark e os resultados obtidos demonstram a utilidade dos métodos. Essa tese introduz um conjunto de algoritmos baseados em grafos para o mapeamento eficiente de circuitos VLSI com células simples. Os algoritmos propostos se baseiam em minimizar de maneira eficiente o número de elementos lógicos usados na implementação do circuito. Posteriormente, uma quantidade significativa de esforço é aplicada na minimização do número de inversores entre esses elementos lógicos. Por fim, essa representação lógica é mapeada para circuitos compostos somente por células NAND e NOR de duas entradas, juntamente com inversores. Células XOR e XNOR de duas entradas também podem ser consideradas. Como nós também consideramos circuitos sequenciais, flips-flops também são levados em consideração. Com o grande esforço de minimização de elementos lógicos, o circuito gerado pode conter algumas células com um fanout impraticável para os nodos tecnológicos atuais. Para corrigir essas ocorrências, nós propomos um algoritmo de limitação de fanout que considera tanto a área sendo utilizada pelas células quanto a sua profundidade lógica. Os algoritmos propostos foram aplicados sobre um conjunto de circuitos de benchmark e os resultados obtidos demonstram a utilidade dos métodos. Adicionalmente, algumas aplicações Morethan-Moore, tais como circuitos baseados em eletrônica impressa, também podem ser beneficiadas pela abordagem proposta. / This thesis introduces a set of graph-based algorithms for efficiently mapping VLSI circuits using simple cells. The proposed algorithms are concerned to, first, effectively minimize the number of logic elements implementing the synthesized circuit. Then, we focus a significant effort on minimizing the number of inverters in between these logic elements. Finally, this logic representation is mapped into a circuit comprised of only two-input NANDs and NORS, along with the inverters. Two-input XORs and XNORs can also be optionally considered. As we also consider sequential circuits in this work, flip-flops are taken into account as well. Additionally, with high-effort optimization on the number of logic elements, the generated circuits may contain some cells with unfeasible fanout for current technology nodes. In order to fix these occurrences, we propose an area-oriented, level-aware algorithm for fanout limitation. The proposed algorithms were applied over a set of benchmark circuits and the obtained results have shown the usefulness of the method. We show that efficient implementations in terms of inverter count, transistor count, area, power and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while (i) optimizing the number of added inverters; and (ii) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation and delay up to 48%, 5%, 5%, 5%, and 53%, respectively. As the adoption of a limited set of simple standard cells have been showing benefits for a variety of modern VLSI circuits constraints, such as layout regularity, routability constraints, and/or ultra low power constraints, the proposed methods can be of special interest for these applications. Additionally, some More-than-Moore applications, such as printed electronics designs, can also take benefit from the proposed approach.