Timing analysis is a key sign-off step in the design of today's chips, but technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models ranging from the basic MOSFET device model to full-chip models of important performance metrics including power, frequency of operation, etc. The assessment of the quality of such models is an important activity, but it is becoming harder and more complex with rising levels of variability and the increase in the number of systematic effects observed in modern CMOS processes. The purpose of this research is (i) to introduce special-purpose test structures that specifically focus on ensuring the accuracy of gate timing models, and (ii) to introduce methods that analyze the extracted information, in the form of path delay measurements, using the proposed test structures. The certification of digital design correctness (the so-called signoff) is based largely on the results of performing Static Timing Analysis (STA), which, in turn, is based entirely on the gate timing models. The proposed test structures compare favorably to alternative approaches; they are far easier to measure than direct delay measurement, and they are much more general than simple ring-oscillator structures. Furthermore, the structures are specified at a high level, allowing them to be synthesized using a standard ASIC place-and-route flow, thus capturing the local layout systematic effects which can sometimes be lost by simpler (e.g., ring oscillator) structures. For the silicon timing analysis, we propose methods that deduce segment delays from the path delay measurements. These estimated segment delays using our methods can be directly compared with the timing models. Therefore, it will be easy to identify the cause of timing mismatches. Deducing segment delays from path delays, however, is not an easy problem. The difficulties associated with deconvolving segment delays from measured path delays come from insufficient sampling points. To overcome this limitation, we first group the segments based on certain characteristics of segments, and adapt Moore-Penrose pseudo-inverse method to approximately solve the segment delays. Secondly, we used equality-constrained least squares methods, which enable us to find a unique and optimized solution of segment delays from underdetermined systems. We also propose another improved test structure that has a built-in test pattern generator, and hence does not require ATPG (Automatic Test Pattern Generation). It is a self-timed circuit, and this feature makes the test structure run as fast as it can. Therefore, measurements can be made under high speed switching conditions. Finally, we can study dynamic effects such as timing effects of different levels of switching activities and voltage drop with the new test structure. / text

In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method. / Master of Science

The model- and component-based development approach has emerged as an attractive option for the development of Distributed Real-time Embedded (DRE) systems. In this thesis we target several issues such as modeling of legacy communication, extraction of end-to-end timing models and support for holistic response-time analysis of industrial component-based DRE systems. We introduce a new approach for modeling legacy network communication in component-based DRE systems. By introducing special-purpose components to encapsulate and abstract the communication protocols in DRE systems, we allow the use of legacy nodes and legacy protocols in a component- and model-based software engineering environment. The proposed approach also supports the state-of-the-practice development of component-based DRE systems. The Controller Area Network (CAN) is one of the widely used real-time networks in DRE systems especially in automotive domain. We identify that the existing analysis of CAN does not support common message transmission patterns which are implemented by some high-level protocols used in the industry. Consequently, we extend the existing analysis to facilitate the worst-case response-time computation of these transmission patterns. The extended analysis is generally applicable to any high-level protocol for CAN that uses periodic, sporadic, or both periodic and sporadic transmission of messages. Because an end-to-end timing model should be available to perform the holistic response-time analysis, we present a method to extract the end-to-end timing models from component-based DRE systems. In order to show the applicability of our modeling techniques and extended analysis, we provide a proof of concept by extending the existing industrial component model (Rubus Component Model), implementing the holistic response-time analysis along with the extended analysis of CAN in the industrial tool suite (Rubus-ICE), and conducting an automotive case study. / EEMDEF

With the high complexity of modern day microprocessors and the slow speed of cycle-accurate simulations, architects are often unable to adequately evaluate their designs during the architectural exploration phases of chip design. This thesis presents the design and implementation of the timing partition of the cycle-accurate, microarchitecture-level SFFSim-Bear simulator. SFFSim-Bear is an implementation of the speculative functional-first (SFF) methodology, and utilizes a hybrid software-FPGA platform to accelerate simulation throughput. The timing partition, implemented in FPGA, features throughput-oriented, latency-tolerant designs to cope with the challenges of the hybrid platform. Furthermore, a fault injection framework is added to this implementation that allows designers to study the reliability aspects of their processors. The result is a simulator that is fast, accurate, flexible, and extensible. / text